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Cliff Hou’s DAC Keynote

Cliff Hou’s DAC Keynote
by Paul McLellan on 06-23-2014 at 10:21 am
Categories: Foundries, TSMC

Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference party where we signed several hundred copies. You can still get a copy if you missed out, just click on the book cover on the top left hand side of the front page of SemiWiki.

Cliff’s keynote was about the future challenges of getting to 10nm and beyond. 14/16nm (they are basically the same despite the different numbers) are pretty much a done deal. Not yet in volume production but on track to get there later this year.

Cliff started by talking about mobile which is what drives semiconductor leading edge processes. Design innovation drives process innovation which enables more design innovation. As a result we have product innovation. It seems like we have always had smartphones but in fact the iPhone only came along 7 years ago. Up until then we had dumbphones although some marketing guy at Nokia cleverly called them feature phones to make them seem…almost smart.

Of course every process generation things get harder. Double patterning, FinFETs, multiple-patterning and so on. The big challenge is that as we approach 10nm, everything becomes more costly and so the economic driver that has been behind the semiconductor industry for the last few decades is weakening. It seems clear that the technical challenges can be overcome but at what cost?

There are two different sets of challenges getting to each new process node: the process issues, mostly around lithography, and the ecosystem issues.

  • lithography: continue to scale 193nm immersion
  • device: continue to deliver 25-30% speed gain at the same or reduced power
  • interconnect: address escalating parasitics
  • production: ramp volume in time to meet end-customer demand
  • shortened development runway to meet product windows

Design and technology co-optimization used to be fairly straighforward. The best local optimum was also the best overall optimum: shortest wire length the best, best gate-density the best area scaling, best technology also best cost. But these rules don’t hold any more. Everything has to be co-optimized from process, EDA tools and IP. If one of these is not up in time then the designs cannot be completed and the fab will not be filled as soon as capacity is available. And given the cost of a fab at $5-8B then a fab that is not full costs a huge amount in depreciation.


The time to get to market is speeding up too. First test chip, first PDK, first shuttle, volume production, the big milestones on a new node are getting compressed. At 10nm, Cliff reckons they will be roughly half the time they had at 28nm. The cost of bringing the process up and building the fabs to run it makes it imperative to start recovering the cost as soon as possible.


Bottom line: this all requires much closer collaboration between all the partners to make everything work in a timely manner. This is the key to unlock 10nm and beyond and turn the vision into reality.


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TSMC (TSM) is Having Another SoC Year!

TSMC (TSM) is Having Another SoC Year!
by Daniel Nenni on 06-18-2014 at 9:00 am
Categories: Foundries, TSMC

TSMC’s stock has more than doubled in the last five years. Coincidentally that is when I started blogging about TSMC. QCOM stock has experienced a similar doubling during this time as have other TSMC customers. The question is: What is next for TSMC? As I have mentioned before, you would be better off taking stock tips from your dog but this is what I see for this year and next for TSM.

Apple will become one of TSMC’s largest customers in 2014. This is simply amazing to me as I grew up with Apple as a computer hobbyist. Apple started selling mother boards before selling complete computer systems. In fact, I was at the UC Berkeley Campus when Steve Jobs entered wearing a backpack with a Macintosh computer inside ushering in a new era of personal computing. And now Apple is one of the largest fabless semiconductor companies? It boggles the mind!

The quarterly wafer ramping numbers I have read for Apple are $0 to $700M per quarter this year starting in Q2 2014 and up from there depending on the success of the iPhone6 and iPads to be announced later this year. As I have mentioned before, I predict that the iPhone6 will break revenue records and it is filled with TSMC silicon, absolutely. Given that TSMC will ship 300,000 20nm wafers in 2014, Apple will probably consume most of them. The other SoC vendors are still scrambling to get 64-bit 20nm SoCs taped-out. Apple really disrupted the SoC business with their 64-bit A7!

In 2015 Apple business could result in an additional $1B per quarter for TSM. Based on what I heard at #51DAC the TSMC/Apple relationship will continue into the FinFET era. One interesting note; I saw quite a few Apple badges at #51DAC, which was not the case at #50DAC. Those Apple engineers are becoming more plentiful and less stealthy it seems.

QCOM however is TSMC’s largest customer. QCOM consumed a record number of wafers last year, roughly a 50% YoY increase. FinFET is the big question, will they go TSMC or Samsung? I can tell you for a fact that QCOM will not use Intel Foundry, nor will any other SoC vendor that has a choice. It may have something to do with Intel flooding the market with free 22nm SoCs? Let’s see how many of those 40 million “contra revenue” parts actually make it into consumer’s hands. Ironically Intel will be using TSMC 28nm for their new Sofia SoC but I would not expect any volumes there either unless Intel goes contra revenue again.

The latest word from #51DAC is that QCOM will straddle TSMC and Samsung for FinFET wafers to get better margins. TSMC’s margins are at an all-time high (36%) and QCOM’s are at an all-time low (16%) so you do the math. A Samsung/QCOM foundry relationship seemed like a natural fit since Samsung is one of QCOM’s largest customers but with the launch of the Samsung Exynos SoC in 2010 the two companies are now frenemies. As they say, keep your friends close but your enemies closer. That is from the book “GodFather II” by the way. Michael Corleone said, “My father taught me many things here — he taught me in this room. He taught me — keep your friends close but your enemies closer.”

The other SoC vendor that I track is MediaTek. They are literally down the street from TSMC and UMC so I see them during my Taiwan travels. MediaTek is an interesting company that has done extremely well in the low end SoC business. I view MediaTek, TSMC, and UMC as brothers so I highly doubt they would use GlobalFoundries or Samsung but it is certainly possible. In this business margins are everything.

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GDS II Online for TSMC

GDS II Online for TSMC
by Paul McLellan on 06-12-2014 at 4:00 pm
Categories: eSilicon, Foundries, Semiconductor Services, TSMC

I just watched an interesting video of a demonstration at DAC of the eSilicon GDS II online quote for TSMC. Actually, it wasn’t so much as a demonstration as an interactive use of the quote tool using data supplied by a member of the audience.

The quote system works for TSMC processes from 28nm up to 350nm. The design the audience member wants quoted is a transceiver in TSMC’s 180nm process, mixed signal variant, with 6 layers of metal. The die size and package are specified (although for some reason that part of the video has been edited out).


A press of a button and the quote is created. It is very detailed.

  • package design $14,270
  • manufacturing services (test harness, probecards etc) $155,817
  • ESD qualification $9.500
  • test development $50,200
  • then there are lots of optional services that are priced such as burn-in, process corner analysis
  • lot buy pricing for 25,12 and 6 wafer lots at $73,866, $38,571 and $19,286 respectively, expected to yield 86,662 die, 41,598 die and 20,799 die
  • respin pricing (for a metal only change using some wafers held back at contact)

Finally the die price which is $2.35 assuming 90% wafer-sort yield (if the yield is 95% then $2.29 and at 85% $2.43).


The entire quote takes a little less than 10 minutes. And it is a quote not an estimate. Provided you don’t change anything (like the die size) then eSilicon stands behind the quote and will deliver all the services at the prices in the quote. Of course under the hood they have a TSMC price model built into the system, but that is transparent to you the customer. eSilicon takes care of all the negotiation with TSMC, the logistics of manufacturing, packaging, test, delivery and the various optional services, if any, that you have requested. Until recently, pricing a design was something that took a couple of weeks, and was anything but transparent. Now eSilicon, with the help of TSMC of course, have made something that used to take several weeks be just a few minutes.

Of course if something does change, for instance the die comes in larger or smaller than forecast when the quote was first done, then it only takes 10 minutes to generate a new quote and eSilicon will stand behind those revised prices. It is a big change from how I remember we used to do quotes when I was in the ASIC business in the 1980s.

Unfortunately eSilicon don’t have all the permissions they need to post the video so I can’t give you a link to it. I guess you just had to be there.


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TSMC vs Intel vs Samsung FinFETs

TSMC vs Intel vs Samsung FinFETs
by Daniel Nenni on 06-08-2014 at 10:50 am
Categories: Foundries, TSMC

By definition the pure-play foundry business model separates the design and manufacturing of a semiconductor device. TSMC was the first dedicated (pure-play) foundry which enabled the incredible fabless semiconductor ecosystem we have today. If not for the fabless business model we would not have the supercomputer class mobile devices in our pockets. We, as integral parts of the fabless semiconductor ecosystem, have changed the world, absolutely.

So the question is: As an executive for a fabless semiconductor company, why would you even consider turning back the clock and renting fab space from an IDM (a company that both designs and manufactures semiconductor devices)?

As a student of history I have always felt that it is critical to understand how you got to where you are today in order to predict where you will be tomorrow. As a 30 year veteran of Silicon Valley I have seen many companies succeed but I have also seen many more fail due to one fundamental truth, they failed at the future. In writing “Fabless: The Transformation of the Semiconductor Industry” Paul McLellan and I both agree that the key to the fabless business model is competition. Unfortunately, at 28nm there was no real foundry competition and that has opened the foundry business doors to IDMs once again.

You can’t fault TSMC. They executed at 28nm and were rewarded with a dominant market position. Had GlobalFoundries been able to provide a competitive 28nm offering I would not be writing this blog. Trust me on this: fabless semiconductor companies would NOT even consider doing business with an IDM foundry if they had two or more leading edge pure-play foundry options.

Intel thinks they are clever by getting into the foundry business. Unfortunately Intel is being used as a pawn in a very high stakes game of foundry chess. I also believe this to be true in the SoC business but that is another blog. Samsung on the other hand is a chess grandmaster which puts Intel between a serious rock (Samsung) and a very hard place (TSMC). Take a close look at Samsung’s latest announcements:

Samsung ♥ GLOBALFOUNDRIES

Samsung Endorses FD-SOI!

Both are excellent moves in becoming an integral part of the fabless semiconductor ecosystem. Samsung is also the only foundry to show working 14nm Silicon at the Design Automation Conference last week. My sources tell me that Samsung 14nm is 3-6 months ahead of TSMC’s 16FF+. My sources also tell me that TSMC 16nm FF+ is today the most competitive FinFET offering, meaning power, performance, area, AND cost. This is based on information from the associated PDKs and not from PowerPoint slides or press releases.

Competition is what drives the fabless semiconductor ecosystem and I thank Intel and Samsung for the investments they have made. If not for that competitive pressure we would not have the ultra-aggressive FinFET process development schedule nor would we have the competitive wafer pricing I have seen of late. Unfortunately all FinFET processes are not created equal so it will be difficult for the fabless companies to design to multiple foundries which mean there will be clear winners and losers in this game. If this was a horse race and I had to make a bet today it would be TSMC to win, Samsung to place, and Intel will not even show. Just my opinion of course.

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TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC

TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC
by Paul McLellan on 05-28-2014 at 8:11 pm
Categories: Foundries, TSMC

What is TSMC doing at DAC?

The biggest event is presumably Cliff Hou’s DAC keynote on Monday at 3.25pm Industry Opportunities in the Sub-10nm Era. And he also wrote the foreword to Fabless, the book that Dan Nenni and I have written and where you can get a signed copy on Tuesday evening at the reception.

There is an IP workshop Driving Quality to the Desktop of the DAC Engineer which takes place on Sunday from 1-5pm in room 202 in the Moscone Center. This is presented by Steven Chen and Lluis Paris.

TSMC is participating in two panels. The first is on the IP track and is in room 101. Lluis Paris is moderating the topic of IP Quality. There is also a pavilion panel on Connecting Everything: Architecting the Internet of Things,Dan K is on the panel.

There are lots of presentations with TSMC’s partners, too many to mention.

TSMC themselves are on booth 1801. They will be talking a lot about IP quality. Have you noticed TSMC are very big on IP quality? They started just using software tools such as Spyglass for evaluating quality but they have now created a silicon validation lab in Taiwan to take it to the next level.


So the top level message is:

  • 20nm Complete

    • In mass production
    • Everything qualified and validated on customer designs
  • 16nm FinFET Complete

    • V1.0 Certification completed
    • IP silicon validated and available
    • Interface IP in silicon validation now
    • 16nm FinFET will be ready by end of year


One new thing you might not have heard is that there is a new 28HPC process offering. Spice corners have been tightened and there is a new signoff methodology. There is also a new high-efficiency 7-track library.

OIP is thriving. It has been running for over 12 years. The portfolio is impressive with over 7000 titles from 40 different IP vendors.


Overview of activities is here. Theater schedule on the booth is here.

Once again, TSMC’s booth is #1801.


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Motley Fools Intel Investors Again!

Motley Fools Intel Investors Again!
by Daniel Nenni on 05-22-2014 at 12:00 pm
Categories: Foundries, Intel Foundry, TSMC

It really is quite a racket. Investor bloggers spread semiconductor disinformation for $.01 per click, that coincidentally covers their stock positions, and I get paid $300 per hour to explain it to Wall Street. While I appreciate the opportunity to bond with the financial people, I do wonder how these bloggers sleep at night.

Here is the latest disinformation from Motley Fool:

While Taiwan Semiconductor (NYSE: TSM ) , Samsung (NASDAQOTH: SSNLF ) , and others have been claiming that everything is going swimmingly for production during 2014, the reality from the semiconductor equipment vendors’ point of view is a different one that should allow Intel (NASDAQ: INTC ) investors to breathe a sigh of relief.

My translation: Please don’t sell your Intel stock until I cover my position. The reality from the semiconductor equipment vendors is that they will miss Wall Street’s expectations so it’s finger pointing time. Just once I would like to hear a CEO on a conference call say, ”You know what, we screwed up, it’s all our fault, we deserve a stock downgrade.”

In short, while TSMC and Samsung talk a big game with respect to their FinFET nodes, the truth is that the foundries are having a difficult time getting the yields to be passable and seem to be quite a way from production. The question, then, is how far from volume production are the foundries?

Wait, did he just call TSMC and Samsung liars? At the 25[SUP]th[/SUP] Annual TSMC Technology Symposium last month customers (close to 1k people I would guess) got a complete update:

TSMC Updates: 20nm, 16nm, and 10nm!

Unfortunately or fortunately only semiconductor professionals were invited so the investor bloggers don’t know any better.

By the way, this particular investor blogger also published this:

Intel’s 14 Nanometer: It’s Here And It Kicks ButtSeptember 15, 2013
At the very first keynote by new Intel (INTC) CEO Brian Krzanich, I had a front row seat to the demonstration of the world’s very first, fully-working 14 nanometer microprocessor. Folks, this isn’t some “test chip”, but a bonafide, fully-functional, Windows-booting microprocessor that is set to go into production by Q4 2013.

Paul McLellan and I sat in the 5[SUP]th[/SUP] row and having published earlier that Intel 14nm would be delayed we were quite shocked. SemiWiki readers know the rest of this story, Brian K. had to eat crow in his next conference call and admit that 14nm would in fact be delayed. The 14nm microprocessor mentioned above is now set to hit shelves by Q4 2014.

So the truth is that Intel was having a difficult time getting the yields to be passable and seem to be quite a way from production.

As I mentioned before, disinformation is a competitive weapon and something publicly traded companies are good at. Most of these investor bloggers are spoon fed PR stuff, they cut and paste the rest to support what’s in the spoon. Add in the personal bias of owning the stock and you get a serious amount of disinformation, which is why Wall Street keeps calling.

Just my opinion of course! :rolleyes:

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TSMC Updates: 20nm, 16nm, and 10nm!

TSMC Updates: 20nm, 16nm, and 10nm!
by Daniel Nenni on 05-05-2014 at 2:30 pm
Categories: Foundries, TSMC

*Spoiler Alert: The Sky is Not Falling*
The TSMC Technology Symposium last month provided a much needed technology refresh to counter aging industry experts (they make their living selling reports) who have been somewhat negative on the future of the fabless semiconductor ecosystem. If the sky wasn’t falling who would buy the reports, right? Let’s take a look at what Handel Jones of IBS reported last year and sync it up with what we learned from TSMC executives and symposium attendees last month.

Handel’s Chicken Little Conclusions:

[LIST=1]

  • 28nm will have a long lifetime with opportunities for equipment vendors to expand capacity inside China
  • 20nm parametric yield will improve and it will be a high volume technology node in 2015 but mostly 2016.
  • 16/14nm will provide low cost gates with volume production only in 2017.
  • 10nm will be postponed. Cost per gate will be prohibitive and unclear where demand will come from outside high-speed processors and FPGAs.

    First: Handel is RIGHT about 28nm having a long lifetime and it just got longer with the announcement by Jean-Marc Chery, COO of ST Microelectronics:

    “We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures the industry of high-volume production of ST’s FD-SOI based IC solutions for faster, cooler, and simpler devices and strengthens the business and financial prospects of the Embedded Processing Solutions Segment.”

    Sources point to SMIC and the expanding low cost China mobile market which makes complete sense if you understand FD-SOI. Handel Jones has a white paper out titled “Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets.“ Paul McLellan wrote about it here. The discussion in the comment section is worth a read, absolutely. Maybe Handel will update that white paper to include 28nm?


    Second: Handel is WRONG about 20nm by one year. According to JK Wang, Vice President of Operations for 300mm fabs, TSMC will ship 300,000 20nm wafers in 2014 and 1,000,000 20nm wafers in 2015. The symposium attendees I spoke with confirmed 20nm is now in production with plenty of time for the holiday gift season.

    Third:Handel is WRONG again about FinFETs by another year. According to JK Wang, 900,000 16nm wafers will ship in 2015 and 1,300,000 wafers will ship 2016. Samsung supports this timeline saying 14nm will be in full production in 2015. And again attendees confirmed this.

    Fourth: Handle is WRONG about 10nm. According to Mark Lui, TSMC President and Co-Chief Executive Officer, 10nm will have multiple customer tapeouts in 2015 and risk production is planned for late 2016. 10nm is expected to provide a 25% performance increase, a 45% power reduction, and a 2.2X gate density increase over 14nm. 10nm will use existing immersion lithography equipment but will be “EUV compatible” if and when EUV is available. According to Paul McLellan, my goto lithography source, EUV is a big fat IF!

    Symposium attendees were a bit more skeptical on 10nm arriving on time but both Samsung and TSMC insist 10nm is well within the 2 year process ramp window. Given the great progress on Gen1 FinFETS I will play along with Gen2 roadmaps for now, absolutely.

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    TSMC Will Own the Internet of Things!

    TSMC Will Own the Internet of Things!
    by Daniel Nenni on 04-27-2014 at 8:00 am
    Categories: Foundries, TSMC

    In my quest to uncover the future of the semiconductor industry I was quite impressed by the executive presentations at the TSMC Symposium last week. Rick Cassidy opened the 20[SUP]th[/SUP] Annual TSMC Technology Symposium followed by Dr. Mark Liu, Dr. Jack Sun, Dr. Cliff Hou, J.K Wang, Dr. V.J. Wu, and Suk Lee. A variety of topics were covered but I had IoT on my mind so that is what I will talk about here.

    Internet of Things (IoT)-The network of physical objects that contains embedded technology to communicate and sense or interact with the objects’ internal state or the external environment.

    My interest in IoT started with chapter 8 of Fabless: The Transformation of the Semiconductor Industry where I asked 30 industry luminaries, “What’s next for the semiconductor industry?” In the 300 word responses IoT was a common thread so that is where I have been spending my time. My goal is to navigate through the hype and figure out just how the fabless semiconductor ecosystem (EDA, IP, Foundries) can monetize this emerging market. The semiconductor industry is all about design starts and to me that is what IoT is all about. From what I can tell, the majority of IoT designs today are implemented in mature nodes with 65nm considered bleeding edge technology.

    The basic building blocks of an IoT chip include:

    • MCU (ARM is the default here)
    • Sensors (temperature, vibration, gyroscope, humidity, pressure, altitude)
    • Power Management (solar, energy harvesting, short burst battery usage)
    • Embedded Memory (flash, NVM, SRAM)
    • Connectivity (GSM, GPRS, LTE, Zigbee, WiFi, Mesh Network)

    Let me know if I’m missing a block.

    According to J.K. Wang, Vice President of Operations of 300mm fabs, TSMC ships more than 1.3M 28nm wafers annually and that will increase by 20% this year. The transition to FinFETs is expected to start in 2015 with 900k wafers shipped followed by 1.3M wafers in 2016 which will free up an amazing amount of low cost 28nm capacity. 28nm also has the strongest design ecosystem with more than 100 partners including 39 vendors offering more than 6,000 pieces of IP. This has the makings of a perfect IoT storm:

    Low Cost + Large Capacity + Low Power + Design Enabled = Low Barrier to Entry!

    The next of many IoT seminars I will attend is sponsored by the World Affairs Council:

    The Internet of Things: Global Implications of Merging the Physical and Digital Worlds

    More than nine billion devices around the world are currently connected to the Internet, including computers and smartphones. That number is expected to increase dramatically within the next decade, with estimates ranging from quintupling to 50 billion devices to reaching one trillion. Please join us for a discussion of how the Internet of Things will impact the way we live, the way business is done and how resources are consumed. Important to the discussion will be the challenges ahead when merging the physical and digital worlds and the implications for privacy and security around the world.

    SPEAKERS:

    MODERATOR:

    • Aleecia McDonald, Director of Privacy, Center for Internet and Society, Stanford Law School

    WHEN:

    Wednesday, May 7, 2014
    Reception: 6:00 PM – 7:00 PM
    Event: 7:00 PM – 8:00 PM

    WHERE:

    Cadence Design Systems, Inc.
    2655 Seely Avenue, San Jose, CA 95134

    I hope to see you there!

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    Dr. Morris Chang: A Conversation with the Chairman

    Dr. Morris Chang: A Conversation with the Chairman
    by Daniel Nenni on 04-24-2014 at 10:00 pm
    Categories: Foundries, TSMC

    There are moments in one’s career that are memorable beyond others, and last night was one of those moments for me, absolutely:

    Stanford University President John L. Hennessy will lead a discussion with Stanford Engineering Hero Morris Chang, an innovator and entrepreneur who revolutionized the semiconductor industry by creating the world’s first dedicated silicon foundry, Taiwan Semiconductor Manufacturing Company or TSMC.

    The NVIDIA Auditorium at the Stanford Huang Engineering Center was filled with semiconductor executives, alumni, and students alike. I don’t know how an invitation made its way into my inbox but I am very appreciative. The conversation was engaging to say the least and quite funny at times.

    Not surprisingly, NVIDIA CEO Jen-Hsun Huang did the introduction and shared some personal stories about Morris. This was reminiscent of the discussionthey had at the Computer Museum seven years ago which was used as research for the soon to be best-selling book Paul McLellan and I wrote.

    Jen-Hsun started out with, “The world is full of successful people but heroes are rare”which I think fits perfectly. He also pointed out that everybody is in possession of two things: Air and products made from TSMC wafers. Jen-Hsun poked good-hearted fun at Morris but the Chairman had the last laugh, definitely.

    The first question from John was if Morris had any idea of the impact TSMC would have on the world. Morris replied that at the time, TSMC was providing a solution that was waiting for a problem since the fabless companies at that time were comfortable with using IDMs for wafer manufacturing. He added that the problems came very quickly and Jen-Hsun was one of those problems! Meaning of course that NVIDIA was a fabless company that was looking for a manufacturing partner with integrity and one they could trust not to compete with them. The laughter in the auditorium acknowledged much more than that of course.

    John’s second question was about TSMC’s focus on R&D. This rings true to me as I see Intel and Samsung spending billions of dollars on marketing obfuscation while TSMC focuses on R&D. The financial ratio I would like to see is R&D/marketing spending knowing full well TSMC would shine.

    The Chairman responded by pointing out he had 30+ years of semiconductor experience (mostly at TI) before starting TSMC . In his words, “You have to climb to the top of a building and look at all of the available roads before you build a new one.” I have climbed a few buildings myself and find this to be very insightful.

    The next question was about the Chairman’s education. Morris spent his first year at Harvard before transferring to MIT to study mechanical engineering. Morris admitted to failing his PhD exam twice at MIT before attending Stanford which again brought laughter. During his career at TI Morris was sent to Stanford to get his PhD in electrical engineering. His career goal was to be CEO, which was not possible at TI, so he joined General Instrument but decided he did not want to be CEO so he founded TSMC.

    The next question was about how TSMC was launched. The Taiwan government was instrumental in funding TSMC providing 48% of the required capital. The additional investments came from Philips Semiconductor and Taiwanese investors who knew little or nothing at all about semiconductors. Morris approached Intel, TI, and semiconductor companies from Japan but they all said no. The Chairman’s memory is clear on this, naming people who actually said no such as Craig Barrett who later became Intel’s CEO.

    The follow-up question was about Japan and why they are no longer major players in the semiconductor industry. According to the Chairman, Japan failed at the future. Instead of embracing the fabless semiconductor business model and unleashing innovation Japan clung to the IDM model and failed. The rest of course is history as most Japanese semiconductor companies are TSMC customers

    The question I had for Morris was if he is working on an autobiography. Morris wrote a book in the 1990s which was quite successful in China. Unfortunately it did not translate well into English so it was not published here. I knew the answer to the question was no before I asked but I wanted to plant the seed anyway. It is a book I would read, absolutely. I would even write it.

    When I decided to write a book my first thought was to write one about Dr. Morris Chang and how he unleashed innovation that changed the world. Friends at TSMC however suggested that I instead write about Morris’s life work which resulted in “Fabless: The Transformation of the Semiconductor Industry”, which is now available on Amazon as a paperback or in Kindle and iBook format on SemiWiki.

    Morris admitted he still smokes a pipe but sited research that says pipe smokers live longer because it helps your mood (laughter). At the end of the event The Chairman was taking pictures with students so I talked to his wife Sophie. Morris always credits her for her support, and one thing I can tell you is that she is as charming as she is beautiful.

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    U2U: Things You Might Not Know About TSMC

    U2U: Things You Might Not Know About TSMC
    by Paul McLellan on 04-10-2014 at 10:50 pm
    Categories: EDA, Foundries, TSMC

    At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee ESD is OK. This is especially critical with FinFET since the transistors are more fragile and have a lower breakdown voltage. There are also decks for 28nm but it is not required (most IP is already in volume production so problems would have shown up by now). The PERC decks guarantee that the ESD rules are all checked without the error-prone process of having to manually add identifying layers. This is the first time TSMC has specified a particular tool that must be used.

    Here is a random miscellany of other facts about TSMC that I picked up:

    • Risk production (samples) for 16FF was at the end of last year
    • Risk production for 10FF will be end of 2015
    • Lots of work has gone on on controlling capacitance on M1 and M2 at 16FF
    • 10nm will have triple patterning and spacer (sidewall image transfer I assume, self-aligned double patterning). More details on 10nm at the TSMC Technology Symposium on 22nd of April
    • TSMC has invested $10B a year for several years to get ready for FinFET
    • FinFET challenges:

      • parasitic capacitance due to the gate wrapping around the fin
      • high parasitic resistance due to local interconnect M0
      • quantized device sizes (only a certain number of fins)
      • breakdown voltage is lower so ESD is more of an issue
    • TSMC has 6600 registered IPs, adding 200 per month

      • 90% hard IP is qualified through IP9000
      • 100% of soft IP is qualified
      • One column on IP listing is (eg) 5/25000 meaning it has been in 5 tapeouts and 25,000 wafers of production
    • Extending from quality audit to slicon validation

      • TSMC has set up validation centere in Taiwan
      • over 20 IPs validated already (started with interface IP)
    • 28nm cycle time started as 4 months, now down to 2 months
    • 16nm cycle time is 5 months will probably end at 3 months
    • Currently 16FF shuttle is about 160 days
    • EUV, TSMC have invested $0.5B in ASML but ROI not good, keeps slipping. They are looking at e-beam and other backup strategies
    • Since EUV is certainly not coming soon, 3D technologies (CoWoS) very important

    What is driving N16FF. Mobile of course. Here are the changes from 2012-2014

    • Display 2X
    • Radio 2X
    • Connectivity 3X
    • AP 2X CPU, 5X GPU and 2X memory bandwidth
    • 2 cores go to 8 cores
    • Power same or less
    • Form factor thinner and lighter
    • Camera 8MP to 13MP

    If you are a TSMC customer you can register for the technology symposium on 4/22 here.
    Details of Mentor’s European U2U in Munich on November 6th is here. You can still submit abstracts until July 1st.


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