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ARM ♥ TSMC!

ARM ♥ TSMC!
by Daniel Nenni on 10-02-2014 at 4:00 pm
Categories: Arm, Foundries, IP, TSMC

This week is the 10[SUP]th[/SUP] annual ARM Technical Conference in Silicon Valley. In regards to size, content, and relevance, I believe ARM TechCon is the #1 event for the fabless semiconductor ecosystem for sure. I attended keynotes, sessions, and walked the hallways on Wednesday and Thursday. I wish I could write about everything I learned but I do have NDA issues with my day job and some of the information needs to be verified by other sources before I can post it.

There were Cadence and Synopsys logos all over the place. I saw Aldec, Apache, Ansys, Calypto, Carbon Design, Dorado, Doulos, and Mentor. And not just Mentor, but my favorite EDA CEO Wally Rhines was walking the conference floor as well. You will not find a more “in touch” EDA CEO than Wally. He doesn’t seem to age either so Mentor probably has some cryogenic projects going on up in Wilsonville.

The foundries were well represented by TSMC, GLOBALFOUNDRIES, STMicro, and Samsung. Wait, where was Intel Custom Foundry? Atmel had a very nice IoT exhibit as did Freescale. Xilinx had a great presence as I mentioned HERE. The IP companies were there in force: Arteris, CEVA, Kilopass, Memoir, Rambus, Silicon Image, Sonics, True Circuits, and a few others. All of the EDA and IP companies were announcing support for TSMC 10nm during the conference. Bottom line is that the fabless semiconductor ecosystem gets stronger every year and will continue to do so.

Also Read: TSMC Delivers First FinFET ARM Based SoC!

The big news for me is the ARM/TSMC 10nm roadmap because let’s face it, the majority of the fabless wafers being shipped today include ARM IP. TSMC transformed the semiconductor industry with the pure-play foundry business model and ARM transformed the microprocessor industry with the IP business model so it makes complete sense for these two industry superheroes to team up on 10nm. Notice that the TSMC event was on Monday and Tuesday of this week and ARM TechCon was Wednesday-Friday.

ARM and TSMC Unveil Roadmap for 64-bit ARM-based Processors on 10FinFET Process Technology

“TSMC has continuously been the lead foundry to introduce advanced process technology for ARM-based SoCs,” said Dr. Cliff Hou, TSMC vice president of R&D. “Together with ARM, we proved out in silicon the high performance and low power of the big.LITTLE architecture as implemented in 16FinFET. Given the successful adoption of our previous collaborative efforts, it makes sense that we continue this fruitful partnership with ARM in future 64-bit cores and 10FinFET.”

I talked to Cliff after the TSMC event on Tuesday about the aggressive 10nm schedule (risk production in Q4 2015). Remember, 20nm risk production was in Q4 2013 and 16nm risk production is happening now (Q4 2014). Never before have we seen such a rapid pace of process development. Intel of course shares credit as their “aggressive” marketing tactics motivated the mighty fabless semiconductor ecosystem like never before, ABSOLUTELY!

More Articles by Daniel Nenni…..

ARM TechCon 2014delivers an at-the-forefront comprehensive forum created to ignite the development and optimization of future ARM-based embedded products. By offering three full days of technical tracks, demonstrations, and industry insight from broad and deep levels of industry-leading companies and innovative start-ups, ARM TechCon remains more than a tradeshow; it is a comprehensive learning environment for the entire embedded community, uniting the software and hardware communities.

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Who Will Lead at 10nm?

Who Will Lead at 10nm?
by Scotten Jones on 09-29-2014 at 4:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

There has been a lot of discussion on SemiWiki lately around 14nm FinFET technology and who really leads and by how much. I thought it would be interesting to review some process metrics for previous technology generation and then make some forecasts around 10nm.

The focus of this article will be Intel, TSMC and Global Foundries/Samsung as the logic volume leaders:

  • Intel is the world’s largest semiconductor and far and away the largest IDM logic producer today.
  • TSMC is the world’s largest foundry
  • Global Foundries is the world’s second largest foundry. We have combined them with Samsung because they are both members of the common platform alliance and closely aligned in process technology. In fact Global Foundries has licensed Samsung’s 14nm FinFET process technology.

The characterization of process density has shifted over the years and nodes have become less reflective of actual feature sizes and density. A more recent metric that Intel has been using is Gate Pitch (GP) multiplied by Metal 1 Pitch (M1P). This same metric has also shown up in a recent paper by the common platform partners disclosing their 10nm process work. GP x M1P will be the metric used for comparison in this paper.

Intel
The following table presents Intel’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 45nm
| style=”width: 61px; height: 17px” | 32nm
| style=”width: 60px; height: 17px” | 22nm
| style=”width: 60px; height: 17px” | 14nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 319
| style=”width: 60px; height: 17px” | 260
| style=”width: 60px; height: 17px” | 220
| style=”width: 60px; height: 17px” | 180
| style=”width: 61px; height: 17px” | 112.5
| style=”width: 60px; height: 17px” | 90
| style=”width: 60px; height: 17px” | 70
| style=”width: 59px; height: 17px” | 55
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 60px; height: 17px” | 0.85
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 61px; height: 17px” | 0.63
| style=”width: 60px; height: 17px” | 0.80
| style=”width: 60px; height: 17px” | 0.78
| style=”width: 59px; height: 17px” | 0.78
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 350
| style=”width: 60px; height: 18px” | 220
| style=”width: 60px; height: 18px” | 210
| style=”width: 60px; height: 18px” | 160
| style=”width: 61px; height: 18px” | 112.5
| style=”width: 60px; height: 18px” | 90
| style=”width: 60px; height: 18px” | 52
| style=”width: 59px; height: 18px” | 38
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.63
| style=”width: 60px; height: 18px” | 0.95
| style=”width: 60px; height: 18px” | 0.76
| style=”width: 61px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 0.80
| style=”width: 60px; height: 18px” | 0.58
| style=”width: 59px; height: 18px” | 0.74
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 111,650
| style=”width: 60px; height: 18px” | 57,200
| style=”width: 60px; height: 18px” | 46,200
| style=”width: 60px; height: 18px” | 28,800
| style=”width: 61px; height: 18px” | 12,656
| style=”width: 60px; height: 18px” | 8,100
| style=”width: 60px; height: 18px” | 3,640
| style=”width: 59px; height: 18px” | 2,101
|-

All of the pitches down through 14nm are based on Intel public disclosures at IEDM and the IDF. The 10nm forecast is based on applying the average shrink ratio from the previous seven process generations.

TSMC
The following table presents TSMC’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 40nm
| style=”width: 61px; height: 17px” | 28nm
| style=”width: 60px; height: 17px” | 20nm
| style=”width: 60px; height: 17px” | 16nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 310
| style=”width: 60px; height: 17px” | 240
| style=”width: 60px; height: 17px” | 160
| style=”width: 60px; height: 17px” | 162
| style=”width: 61px; height: 17px” | 122
| style=”width: 60px; height: 17px” | 87
| style=”width: 60px; height: 17px” | 90
| style=”width: 59px; height: 17px” | 70
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.77
| style=”width: 60px; height: 17px” | 0.67
| style=”width: 60px; height: 17px” | 1.01
| style=”width: 61px; height: 17px” | 0.75
| style=”width: 60px; height: 17px” | 0.71
| style=”width: 60px; height: 17px” | 1.03
| style=”width: 59px; height: 17px” | 0.78
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 340
| style=”width: 60px; height: 18px” | 240
| style=”width: 60px; height: 18px” | 180
| style=”width: 60px; height: 18px” | 128
| style=”width: 61px; height: 18px” | 95
| style=”width: 60px; height: 18px” | 67
| style=”width: 60px; height: 18px” | 64
| style=”width: 59px; height: 18px” | 46
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.71
| style=”width: 60px; height: 18px” | 0.75
| style=”width: 60px; height: 18px” | 0.71
| style=”width: 61px; height: 18px” | 0.74
| style=”width: 60px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 1.00
| style=”width: 59px; height: 18px” | 0.72
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 105,400
| style=”width: 60px; height: 18px” | 57,600
| style=”width: 60px; height: 18px” | 28,800
| style=”width: 60px; height: 18px” | 20,736
| style=”width: 61px; height: 18px” | 11,590
| style=”width: 60px; height: 18px” | 5,829
| style=”width: 60px; height: 18px” | 5,760
| style=”width: 59px; height: 18px” | 3,220
|-

In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nnm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm.

We have updated this article with actual measured 28nm and 20nm pitch numbers from Chipworks. At 16nm the pitches are based on TSMC’s 2013 IEDM paper. TSMC’s 16nm is reported to have the same metal pitches as their 20nm so we have used the same pitch for 20nm M1. The 16nm gate pitch is larger than our projected gate pitch for 20nm, this is due to the planar to FinFET transition. The 10nm pitches are based on the average TSMC shrink ratios through 20nm. We have excluded 16nm due to the metal pitch pause and planar to FinFET transition.

Global Foundries/Samsung (GF/S)
The following table presents GF/S’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 40nm
| style=”width: 61px; height: 17px” | 28nm
| style=”width: 60px; height: 17px” | 20nm
| style=”width: 60px; height: 17px” | 14nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 350
| style=”width: 60px; height: 17px” | 245
| style=”width: 60px; height: 17px” | 200
| style=”width: 60px; height: 17px” | 129
| style=”width: 61px; height: 17px” | 90
| style=”width: 60px; height: 17px” | 64
| style=”width: 60px; height: 17px” | 78
| style=”width: 59px; height: 17px” | 64
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.70
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 60px; height: 17px” | 0.65
| style=”width: 61px; height: 17px” | 0.70
| style=”width: 60px; height: 17px” | 0.71
| style=”width: 60px; height: 17px” | 1.22
| style=”width: 59px; height: 17px” | 0.82
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 350
| style=”width: 60px; height: 18px” | 245
| style=”width: 60px; height: 18px” | 180
| style=”width: 60px; height: 18px” | 117
| style=”width: 61px; height: 18px” | 96
| style=”width: 60px; height: 18px” | 64
| style=”width: 60px; height: 18px” | 64
| style=”width: 59px; height: 18px” | 48
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 0.73
| style=”width: 60px; height: 18px” | 0.65
| style=”width: 61px; height: 18px” | 0.82
| style=”width: 60px; height: 18px” | 0.67
| style=”width: 60px; height: 18px” | 1.00
| style=”width: 59px; height: 18px” | 0.75
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 122,500
| style=”width: 60px; height: 18px” | 60,025
| style=”width: 60px; height: 18px” | 36,000
| style=”width: 60px; height: 18px” | 15,093
| style=”width: 61px; height: 18px” | 8,640
| style=”width: 60px; height: 18px” | 4,090
| style=”width: 60px; height: 18px” | 4,992
| style=”width: 59px; height: 18px” | 3,072
|-

We do not have actual pitch numbers for GF/S 20nm technology and we have interpolated them based on available data. At 14nm and 10nm the pitches are based on published values including the 2014 VLSIT 10nm paper from IBM, Samsung, St Micro and Global Foundries.

Density Comparisons
Having reviewed the three companies/groups we can now compare the GP x M1P metric over the range of nodes studied.

[TABLE] border=”1″
|-
| style=”width: 61px; height: 19px” |
| style=”width: 71px; height: 19px” | 130nm
| style=”width: 55px; height: 19px” | 90nm
| style=”width: 58px; height: 19px” | 65nm
| style=”width: 70px; height: 19px” | 45/40nm
| style=”width: 70px; height: 19px” | 32/28nm
| style=”width: 70px; height: 19px” | 22/20nm
| style=”width: 70px; height: 19px” | 16/14nm
| style=”width: 70px; height: 19px” | 10nm
|-
| style=”width: 61px; height: 19px” | Intel
| style=”width: 71px; height: 19px” | 111,650
| style=”width: 55px; height: 19px” | 57,200
| style=”width: 58px; height: 19px” | 46,200
| style=”width: 70px; height: 19px” | 38,800
| style=”width: 70px; height: 19px” | 12,656
| style=”width: 70px; height: 19px” | 8,100
| style=”width: 70px; height: 19px” | 3,640
| style=”width: 70px; height: 19px” | 2,101
|-
| style=”width: 61px; height: 19px” | TSMC
| style=”width: 71px; height: 19px” | 105,400
| style=”width: 55px; height: 19px” | 57,600
| style=”width: 58px; height: 19px” | 28,800
| style=”width: 70px; height: 19px” | 20,736
| style=”width: 70px; height: 19px” | 11,590
| style=”width: 70px; height: 19px” | 5,829
| style=”width: 70px; height: 19px” | 5,760
| style=”width: 70px; height: 19px” | 3,220
|-
| style=”width: 61px; height: 19px” | GF/S
| style=”width: 71px; height: 19px” | 122,500
| style=”width: 55px; height: 19px” | 60,025
| style=”width: 58px; height: 19px” | 36,000
| style=”width: 70px; height: 19px” | 15,093
| style=”width: 70px; height: 19px” | 8,640
| style=”width: 70px; height: 19px” | 4,090
| style=”width: 70px; height: 19px” | 4,992
| style=”width: 70px; height: 19px” | 3,072
|-

This table has been updated since the original post based on measured TSMC 28nm and 20nm pitches from Chipworks. In the table above I have marked in bold the densest process at each node. It is interesting to see that it has moved around from node to node. Based on what has been disclosed to date and reasonable projections it looks like Intel will have the densest process at 16/14nm and 10nm using the GP x M1P metric. Whether this translates into a denser process for actual designs is a different question but GP x M1P is in our opinion a good measure of pure process density.

The same data is also plotted below as the now infamous Intel density comparison:

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TSMC Delivers First FinFET ARM Based SoC!

TSMC Delivers First FinFET ARM Based SoC!
by Daniel Nenni on 09-25-2014 at 9:00 am
Categories: Foundries, TSMC

Right on cue, TSMC announces 16nm FinFET production silicon. I believe this is the original version of FinFET versus 16FF+ which is due out in 1H 2015. I will confirm this next week at the TSMC OIP event in San Jose, absolutely. Either way this is excellent news for the fabless semiconductor ecosystem and I look forward to the first tear down of a TSMC FinFET SoC in comparison to an Intel FinFET SoC. TSMC 20nm compared quite favorably against Intel 14nm in regards to density and 16FF will do even better.

Let’s not forget that The Chairman (TSMC’s Dr. Morris Chang) speculated that TSMC would not win a majority FinFET market share in 2015. To me this was a head fake to rally the troops. Morris has done this before on conference calls, he is a very clever man. As I mentioned previously, I have never seen TSMC more energized during my last Taiwan trip. Hschinsu on a whole was really buzzing with activity and it was all about FinFETs no matter where I went.

HSINCHU, Taiwan, R.O.C., Sept. 25, 2014 /PRNewswire/ — TSMC (TWSE: 2330, NYSE: TSM) today announced that its collaboration with HiSilicon Technologies Co, Ltd. has successfully produced the foundry segment’s first fully functional ARM-based networking processor with FinFET technology. This milestone is a strong testimonial to deep collaboration between the two companies and TSMC’s commitment to providing industry-leading technology to meet the increasing customer demand for the next generation of high-performance, energy-efficient devices.

For those of you who don’t know, HiSilicon is the ASIC design division of communications giant Huawei. I first encountered HiSilicon in 2008 during an IP licensing negotiation involving SMIC. More recently I visited the new HiSilicon design center in Taiwan. You will be hard pressed to find a leading SoC company without a design center near Hsinchu so they can seamlessly integrate with TSMC. HiSilicon has 100+ people there now and I’m told they are still hiring.

“Our FinFET R&D goes back over a decade and we are pleased to see the tremendous efforts resulted in this achievement,” said TSMC President and Co-CEO, Dr. Mark Liu. “We are confident in our abilities to maximize the technology’s capabilities and bring results that match our long track record of foundry leadership in advanced technology nodes.”

The other interesting thing about this design is that it uses 3D IC packaging combining 28nm mixed signal and 16nm logic chips. TSMC calls this CoWoS (Chip-On-Wafer-On-Substrate) which allows you to integrate multiple chips into a single device. We have written aboutCOWOS many times before and this is an excellent example. To save time and minimize cost you can integrate 28nm blocks with leading edge CPUs for your SoC.

“We are delighted to see TSMC’s FinFET technology and CoWoS[SUP]®[/SUP]solution successfully bringing our innovative designs to working silicon,” said HiSilicon President Teresa He.”This industry’s first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz. This networking processor’s performance increases by three fold compared with its previous generation. Such a highly competitive product can support virtualization, SDN and NFV applications for next-generation base stations, routers and other networking equipment, and meet our time-to-market goals.”

Congratulations to TSMC, HiSilicon, and the entire fabless semiconductor ecosystem for this incredible achievement. And for those who predicted that fabless FinFET chips would “Happen in 2016 at the earliest or never at all”… There are no words left for you.

Also Read: Intel’s 35% Density Advantage Claim Explored

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The TSMC iPhone 6!

The TSMC iPhone 6!
by Daniel Nenni on 09-23-2014 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

Fortunately Paul McLellan and I missed IDF. Paul was atop Mt. Kilimanjaro and I was in Taiwan signing books. After reviewing the materials and watching the videos we really didn’t miss much in regards to mobile so no regrets. The Apple event would have been fun even though I won’t be buying an iPhone6 or an iWatch and I will tell you why.

In case you missed it, the first iPhone 6 tear down is up on iFixit and surprise-surprise it is filled with silicon from TSMC’s customers (Apple A8, Qualcomm: modem, PM IC – RF transiever – LTE receive and envelope tracking, Murata wifi module, Broadcom touchscreen controller, NXP NFC, and chips from Skyworks, InvenSense, Avago and TriQuint). The absence of Samsung silicon was not a surprise however and it supports my theory that, given the choice, fabless companies will partner with pure-play over IDM foundries, absolutely. The fact that Samsung and Apple have intellectual property issues and Samsung has constant anti Apple advertisements probably does not help either but that comes with competing with your customers I suppose.

Also Read: Intel Core M vs Apple A8!

14nm may be a different story. Intel 14nm did not fit Apple’s requirements so they must choose between TSMC and Samsung or more than likely use a combination of both. 10nm will also be a different story as I have seen the Intel Foundry people at Apple and have heard tales of them aggressively pushing 10nm foundry services. Unfortunately, Intel corporate is still saying they have a 2-3 year lead on 10nm over the foundries and a 45% density advantage which is not true at all. As I mentioned before, the foundries are on schedule for 10nm product tape-outs in Q4 2015. Intel may have 10nm silicon out by then but I highly doubt it will be from foundry customers and the claimed 45% density advantage at 10nm is absolute nonsense. This goes against Intel’s credibility and trust is a significant factor when fabless companies choose a foundry partner, believe it.

Today, Intel Custom Foundry is suffering the same challenge as Samsung Foundry. Other groups within these companies are pissing off the fabless semiconductor ecosystem. This same thing happened at the start of the fabless revolution. The first fabless companies rented space from IDMs but when they started to need more fab space or once they started competing with the IDMs the relationship soured. As a result, the pure-play foundry model became dominant and the rest is history.

In regards to the iPhone6, I find it funny that we worked so hard to make things smaller and now they are getting bigger! I don’t wear a watch so unless the iWatch does something truly amazing I don’t want the additional interrupts. The problem I have with the iPhone6 is the processor speed. I expected the dual cores to clock in at 2GHz versus the paltry 1.4GHZ. The A6 is 1.3GHz, the A7 is 1.3GHz, and the A8 is 1.4GHz. The A7 jumped from 32 to 64-bit so I can understand the comparable GHz but what is the A8’s excuse?

I think I know but I would like to hear your theories in the comment section before I share mine.

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Intel’s 35% Density Advantage Claim Explored

Intel’s 35% Density Advantage Claim Explored
by Daniel Nenni on 09-20-2014 at 1:00 pm
Categories: Foundries, Intel Foundry, TSMC

The previous blog I did on the density difference between Intel 14nm and TSMC 20nm caused quite a stir and many interesting comments which I would like to address. After writing thousands of blogs on a wide variety of topics I have found that playing the devil’s advocate stimulates the most productive conversations and in this case it proved to be true. The Intel Core M vs Apple A8! blog went viral last week and resulted in some very interesting points made in the comment section that I feel should be explored in greater detail.

First is how we measure density. The semiconductor industry is all about packing more transistors in a smaller space. It is part of Moore’s Law, it is how we get less expensive consumer electronics, it is a badge of honor really. There are two transistor numbers you can use: the number of transistors in a design schematic and the number of transistors in the final layout which is then manufactured. The difference between these numbers varies but after taking a quick poll amongst leading edge design and layout people the range is 0-10% more transistors in the layout. Since density is a badge of honor most companies use the layout transistor count but if it serves a marketing purpose they will use the schematic transistor count. Either way, considering the point I’m trying to make, it doesn’t really matter.

Second, comparing the Intel Core M processor and the Apple A8 SoC is like comparing an orange to an apple but this is the only data we have today and it is a good starting point for a density discussion. The architectures are different (CPU vs SoC), the processes are different (20nm planar vs 14nm FinFET), and the companies are very different (IDM versus Fabless).

Third, the performance, power, and functionality of the chips are not part of this discussion. Tear downs and third party benchmarks will be required and they are not available yet. When they are, we can look back on this discussion and see if we were right and if not we can see where we went wrong. All in the interest of science, right?

Here is the argument: Intel claimed a 35% density advantage over TSMC during their November 2103 Investor Meeting using the middle slide above. Intel also used the Altera slide as support for their claim. TSMC rebuffed that claim during a quarterly conference call using the slide on the left.

According to Apple the A8, which is manufactured by TSMC on a 20nm planar process, has about 2B transistors on a 89mm2 die. According to Intel the Core M manufactured on a 14nm FinFET process has about 1.3B transistors on an 82mm2 die.

Given that:

[LIST=1]

  • According to TSMC, 16nmFF+ has a 15% density advantage over 20nm planar
  • We do not know what type of transistor count Intel and Apple uses but assume the worst case with a 10% variance (upsize Intel by 10%)

    Intel’s 35% density advantage claim just does not hold up, not even close. Time will tell, silicon does not lie, but for now TSMC’s density slide is much more honorable than Intel’s. And let’s not forget that Intel’s processes are highly specialized for a single product and TSMC’s processes serve a much wider range of applications. If true, this lack of density gap is really big news for the fabless semiconductor ecosystem, absolutely!

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    TSMC OIP: Registration Open

    TSMC OIP: Registration Open
    by Paul McLellan on 09-06-2014 at 9:00 am
    Categories: Foundries, TSMC

    It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event. More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

    Registration is now open.

    The schedule is as follows:

    • 8.00: registration opens
    • 9.00: welcome remarks
    • 9.20: industry overview and corporate updates
    • 9.50: TSMC and the ecosystem for innovation
    • 10.15: feature talk with ARM
    • 10.45: coffee break

    Then at 11am the forum splits into 3 parallel tracks: an EDA track, an IP track and an EDA/IP/services track. There will be a break for lunch from 12pm to 1pm. Many of the presentations feature both a design partner of TSMC and an EDA or IP partner. Several of the presentations are on 16FF and 10FF, so this is an opportunity to hear about the experience of TSMC’s partners on the most advanced nodes. In particular, from 4pm until the end of the afternoon on the EDA track Cadence will be talking about various aspects of 16FF and 10FF design. Synopsys and Mentor are also presenting on aspects of 16FF.

    The EDA track features presentations from:

    • AMCC/Cadence
    • Synopsys (several)
    • Qualcomm/Mentor
    • Cadence (several)
    • Mentor/TSMC
    • Mediatek/Synopsys

    The IP track features presentations from:

    • Semtech/Snowbush
    • GUC
    • ARM
    • Kilopass
    • Cadence
    • CEVA
    • ARM (several)
    • Imagination
    • Synopsys

    The EDA/IP/services track features presentations from:

    • GUC
    • Lorentz/Altera
    • eSilicon
    • Synopsys
    • Uniquify
    • Oracle/Mentor
    • ANSYS (Apache)
    • Analog bits
    • M31 Technology
    • Microchip SSTI

    The day concludes with a social hour from 5.30pm to 6.30pm.

    If you are doing design with TSMC (and its almost a case of who isn’t?), and especially if you are about to start on a 16FF design, then you should definitely plan to attend. I think the agenda contains a wealth of interesting sounding experience from design groups working right on the bleeding edge.

    Full details of the agenda are here. Registration is here.

    More articles by Paul McLellan…

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    Granite River Labs and TSMC Expand Agreement

    Granite River Labs and TSMC Expand Agreement
    by Paul McLellan on 08-28-2014 at 7:01 am
    Categories: Foundries, TSMC

    For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to recover the huge capital investment a modern fab entails. With many SoCs having over a hundred IP blocks, getting the IP qualified is an essential part of a design team being able to get a design into production. Taking a systematic approach to IP quality is paramount for successful SoC products.


    TSMC’s latest IP validation has multiple steps, increasingly expensive to execute but with increasing confidence level in the IP. The first 3 steps are a review of the IP without manufacturing it. The later steps involve running extensive tests on IP that has been manufactured, typically in a shuttle run for a new process that is not yet in volume production. For more mature processes where a lot of IP has been in use for many years, the sheer number of designs in successful volume production is its own guarantee of IP quality.

    [LIST=1]

  • Physical review (DRC, LVS, ERC, antenna checks)
  • DFM compliance (DFM-LPE, LPC, dummy fill, VCMP)
  • Pre-silicon assessment (design kit review, design review)
  • Silicon assesment (tapeout review, silicon report review)
  • Split lot silicon assessment (split lot tapeout and report review)
  • IP Validation Center (audit IP testing results by TSMC test lab)
  • Volume production

    Last month, TSMC’s IP Validation Center and Granite River Labs deepened their relationship and further expanded the TSMC9000 IP validation ecosystem. This covers expanded test capacity, test auditing and posting IP validation results on TSMC-online. This is a part of item #6 above, leveraging the expertise of GRL in the test and validation of high speed interfaces.

    GRL will serve as an IP validation partner to TSMC. The test methodology development and correlation will be done at GRL’s office in Hsinchu (where TSMC is headquartered of course). The bulk of the work will be carried out at GRL in Santa Clara and Bangalore. TSMC will subcontract to GRL to create a test methodology for the specific PHY. GRL can then use their extensive expertise and wide range of costly equipment to perform the testing. The results will then be available through TSMC-online like where it can be searched by potential users.


    GRL has extensive electrical test facilities using Introspect, Teledyne Lecroy, Tektronix, Keysight and others. They also hav protocol test solutions that can handle error injection, stress testing, protocol exerciser automation and so on. They have R&D sites in Oregon and Japan. Labs in Santa Clara, Bangalore, Penang, Hsinchu and Taipei. The Asian HQ is in Singapore, worldwide HQ is in Silicon Valley.


    More articles by Paul McLellan…

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    When TSMC advocates FD-SOI…

    When TSMC advocates FD-SOI…
    by Eric Esteve on 08-14-2014 at 1:00 pm
    Categories: FD-SOI, Foundries, STMicroelectronics, TSMC

    I found a patent recently (May,14 2013) granted to TSMC “Planar Compatible FDSOI Design Architecture”, the following sentences, directly extracted from this patent, advertise FDSOI design better than a commercial promotion! “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.” Nothing new here for Semiwiki readers… except that this enumeration of the advantages of SOI technology in respect with bulk planar is coming from TSMC…


    In fact, the sentence mention “SOI substrates”, but when you look at the next paragraph, you find the definition of partially-depleted (PD) SOI transistor and fully-depleted (FD) SOI transistor, and their respective behavior and advantages:

    • A PDSOI transistor is formed in an active region with an active layer thickness that is larger than the maximum depletion width. The PDSOI transistor therefore has a partially depleted body. PDSOI transistor have the merit of being highly manufacturable, but they suffer from floating body effects. Digital circuits, which typically have higher tolerance for floating body effects may employ PDSOI transistors.
    • A FDSOI transistor is formed in an active region with an active layer thickness that is smaller than the maximum depletion width. FDSOI transistors avoid problems of floating body effects with the use of a thinner active layer thickness or a lighter body doping. Generally, analog circuitry performs better when designed using FDSOI devices than using PDSOI devices.

    To illustrate this patent, TSMC is referring to a Baseband IC for mobile application, or maybe an integrated BB and Application Processor. In both cases many of the integrated IP, like memory cell or high speed SerDes, are based on analog circuitry, thus FDSOI clearly appears to be the best choice.


    You may wonder why TSMC is highly promoting FDSOI, as we know that the foundry has not selected this technology. TSMC is supporting 28nm bulk planar, then 20nm (including double patterning for critical layers) and 16nm FinFET. So, why TSMC is doing such an advertising for FDSOI? Reading further, we can see:

    “An FDSOI ASIC design in the same footprint as a bulk planar ASIC design provides several advantages over the bulk planar ASIC design. Adaptive body bias techniques are inefficient with bulk planar designs because of the PN junction forward bias issue and because junction leakage increases in the reverse bias condition. Therefore, planar technologies have to adopt voltage scaling techniques for power savings in single Vt designs.”

    It look like that TSMC is willing to demonstrate that a FDSOI design can be portable to a bulk planar technology, providing that the power rails have been carefully designed, and this requirement is extensively described within the patent (in fact, it’s the core of the patent). We have highlighted in Semiwiki one of the important advantages linked with FDSOI technology: a dual Vt library can support a complete SoC design, allowing cost savings (number of masks and process steps is lower) and faster process turnaround time, when compared with four Vt on bulk planar, only bulk option to offer the same level of power savings than FDSOI.

    But we still don’t know why TSMC has filled this patent. Is it because the company is willing to offer FDSOI as an additional process option to existing customers? In this case, this patent could be a way to minimize risk, showing to a customer moving to FDSOI that he could decide to come back to a bulk planar option, with no redesign because the “FDSOI ASIC design is in the same footprint as a bulk planar ASIC design”. By the way, TSMC offering FDSOI process option would be a scoop…

    Another possibility would be that TSMC is not willing to support FDSOI, but certain existing ASIC customer willing to try FDSOI with TSMC competition, this patent would allow TSMC to keep the door opened, and these customers could come back to bulk planar ASIC processed at TSMC. This approach would be like a double sourcing, but between bulk planar and FDSOI.

    TSMC has certainly carefully looked at FDSOI as a technology option, even if so far the company doesn’t support FDSOI. I am happy to see that a TSMC patent highlights the many technical advantages of FDSOI vs bulk planar, like absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance. In this advantage list, we can add potential cost savings (when SOI wafer price will go down), faster wafer fab cycle time and probably the most important, far better power efficiency, whether the SoC is designed for Networking infrastructure or mobile application processor. Will all these advantages be enough to compensate some current weaknesses, like customer fear in front of innovation and work in progress IP ecosystem, and finally pushing TSMC to join the ST and Samsung train?

    From Eric Esteve from IPNEST

    More Articles by Eric Esteve…..

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    Intel Versus TSMC 14nm Processes

    Intel Versus TSMC 14nm Processes
    by Scotten Jones on 08-13-2014 at 5:00 pm
    Categories: Foundries, Intel Foundry, TSMC

    Intel has begun to release some details on their 14nm process. I thought it would be interesting to contrast what Intel has disclosed to TSMC’s 16nm process disclosure from last year’s IEDM (TSMC calls their 14nm process 16nm).

    [TABLE] align=”center” border=”1″
    |-
    | style=”width: 141px” |
    | style=”width: 163px” | Intel 14nm
    | style=”width: 168px” | TSMC 16nm
    | style=”width: 116px” | Ratio TSMC/Intel
    |-
    | style=”width: 141px” | Process target
    | style=”width: 163px” | MPU
    | style=”width: 168px” | SOC
    | style=”width: 116px” |
    |-
    | style=”width: 141px” | Status
    | style=”width: 163px” | Shipping
    | style=”width: 168px” | Development
    | style=”width: 116px” |
    |-
    | style=”width: 141px” | Process type
    | style=”width: 163px” | FinFET on bulk
    | style=”width: 168px” | FinFET on bulk
    | style=”width: 116px” |
    |-
    | style=”width: 141px” | Gate
    | style=”width: 163px” | Gate last HKMG
    | style=”width: 168px” | Gate last HKMG
    | style=”width: 116px” |
    |-
    | style=”width: 141px” | Fin pitch
    | style=”width: 163px” | 42nm
    | style=”width: 168px” | 48nm
    | style=”width: 116px” | 1.14
    |-
    | style=”width: 141px” | Gate pitch
    | style=”width: 163px” | 70nm
    | style=”width: 168px” | 90nm
    | style=”width: 116px” | 1.29
    |-
    | style=”width: 141px” | M1 pitch
    | style=”width: 163px” | 52nm
    | style=”width: 168px” | 64nm
    | style=”width: 116px” | 1.23
    |-
    | style=”width: 141px” | SRAM cell size
    | style=”width: 163px” | 0.0588um2
    | style=”width: 168px” | 0.07um2
    | style=”width: 116px” | 1.19
    |-

    There are both similarities and differences between the processes. Intel’s process is for MPUs and TSMC’s process is for SOCs. MPU processes are more targeted and require fewer options. A TSMC SOC process for example would typically have 2 or more gate oxide thicknesses with options for 4 or more Vts while Intel’s MPU processes are single gate oxide and at 22nm were 3Vts. On the other hand Intel is now shipping 14nm MPUs while TSMC will not be shipping SOCs on 16nm until mid-next year (although Intel will likely not ship their SOC version of 14nm until next year either). Intel’s disclosure also shows a significant density advantage over TSMC at almost 20% for SRAM cell size.

    Also read:Who Will Lead at 10nm?

    The preceding numbers are all based on TSMC’s IEDM paper from last December. TSMC is also known to have an FF and FF+ process. The FF+ process shows significant improvements in performance over FF. Is this due to a shrink or what performance enhancement is used to achieve this? It will also be interesting to see how Samsung’s 14nm process compares once we have critical dimensions for them. I would be very interested to hear from any Semiwiki readers who can provide additional information on the TSMC or Samsung processes.

    A critical metric for both processes will be cost. Intel has already disclosed that 14nm produces a significant cost reduction per transistor versus 22nm (at least for MPUs). Various industry observers have published articles projecting increased cost per transistor for foundries at both 20nm and 16nm/14nm. Our modeling suggests TSMC will achieve a cost reduction at 20nm and may achieve a small cost reduction at 16nm as well.

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    Should we pay the price of Innovation?

    Should we pay the price of Innovation?
    by Eric Esteve on 08-08-2014 at 8:00 pm
    Categories: Foundries, GlobalFoundries, TSMC

    I agree that this question sounds stupid: nobody is forcing me to buy an innovative product, or even a gadget, if I don’t want to pay a high price, I just don’t buy the product. But it seems that some people don’t really think that way. The story is related to Qualcomm sales in China, and recently announced partnership with SMIC…

    The Partnership (the fact)

    From the joint Press Release: SAN DIEGO – July 03, 2014 – Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) and Qualcomm Incorporated (NASDAQ: QCOM), have announced that SMIC and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, are working together in connection with 28nm process technology and wafer manufacturing services in China to manufacture Qualcomm® Snapdragon™ processors. Qualcomm Technologies’ Snapdragon processors are purpose built for mobile devices. SMIC is one of China’s largest and most advanced semiconductor foundries, and Qualcomm Technologies is one of the world’s largest fabless semiconductor vendors and a world leader in 3G, 4G and next-generation wireless technologies. This collaboration will help accelerate SMIC’s 28nm process maturity and capacity, and will also make SMIC one of the first semiconductor foundries in China to offer production locally for some of Qualcomm Technologies’ latest Snapdragon processors on 28nm node, both PolySiON (PS) and high-K dielectrics metal gate (HKMG).

    This PR sounds like both companies are enjoying a new partnership, maybe showing that one of the partners is getting higher benefit: “This collaboration will help accelerate SMIC’s 28nm process maturity and capacity, and will also make SMIC one of the first semiconductor foundries in China to offer production locally for some of Qualcomm Technologies’ latest Snapdragon processors on 28nm node…”. If you further analyze, “Qualcomm will help SMIC accelerate 28nm process maturity” sounds like the customer is devoting resources to help the supplier filling the technology gap with foundry competitors. If you prefer, this PR sounds like Qualcomm is paying an entry ticket to stay active and continue to sale Snapdragon on the Chinese market. Maybe this deal does not look any more like a win-win deal? The good question is to know why Qualcomm had to sign such a partnership?

    I found a possible answer in this article from Junko Yoshida, Chief International Correspondent, EETimes “China’s SMIC-Qualcomm 28-nm Deal: Why Now? “, here is an extract:

    Antitrust investigation in China
    Since China launched an antitrust probe into Qualcomm late last year, speculation abounds that Chinese authorities are probing ways to coerce Qualcomm into collaborating with their electronics industry.
    Qualcomm reportedly faces penalties that may exceed $1 billion. The National Development and Reform Commission (NDRC), China’s main planning body, raided Qualcomm’s Beijing and Shanghai offices last year.
    The NDRC has used the anti-monopoly law to target technology companies for practices that could lead to what it calls “unreasonably” high prices. In February, the Chinese regulator said it suspects Qualcomm of overcharging and abusing its market position.

    So the Chinese regulator (NDRC) considers that technology companies like Qualcomm are selling at “unreasonably” high prices. Let’s make a point: Qualcomm has invented and patented innovative modem techniques (CDMA and the like) for wireless communication, and these techniques have been selected by the telecommunication regulators in the USA (and other regions) to be at the hearth of the new standards. Qualcomm has a de facto monopoly, this is due to the international patent policy: every chip maker developing a modem has to pay a license and royalties to QCOM, and this gives a competitive advantage to Qualcomm when the company also develop modem IC. Qualcomm has been smart enough to also dominate the Application Processor market. The chip maker has just do a better job that TI, Nvidia, Marvell, Freescale… you name it. The equation is rather simple:

    Innovation (Patent) + Investment (IC design) + Roadmap = Strong Leader position

    As far as I am concerned, I don’t see any malfeasance in this strategy. We have seen in the past a high tech PC chip maker basing the company development, not only on a quasi-monopoly (leaving just enough room for a single competitor to survive, so the monopoly was not 100%), but also on anti-competitive practices (like paying back customers to make sure these will stay). Such a behavior has been sanctioned by the American law, and this was good decision. But the picture is completely different with Qualcomm. If you agree with the international patent policy, you must admit that a company cleaver enough to create innovation and turn it into a new technology and the related (IC) products should be in a position to harvest and get benefit from this innovation…

    Let’s make it clear: I have no negative a-priori against China. But I may have a certain reluctance when I see politician (from any country) trying to squeeze innovation. At the end of the day, SMIC will get benefit from this partnership, detrimental to TSMC, Samsung or GloFo, and detrimental also to innovation.

    Eric Esteve

    More Articles by Eric Esteve…..