By Jeff Wilson, Mentor Graphics and Anderson Chiu, TSMC

At this year’s TSMC Open Innovation Platform® (OIP) Ecosystem Forum, Mentor Graphics and TSMC co-presented some results of the ECO Fill flow developed for TSMC customers working at advanced nodes. Here is a summary of the presentation. (TSMC customers can access the presentation at TSMC-Online).

Metal fill (inactive metal shapes) was originally added to open design areas in layouts because a certain metal density was required to pass the foundry’s density design rule checks (DRC). These foundry density requirements helped reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes. To avoid creating parasitic capacitance issues, the goal was to add only as much fill as needed to satisfy the minimum and maximum density requirements set by the foundry.

At 45nm and below, metal fill affects multiple manufacturability issues such as stress, etch response, and rapid thermal annealing, and has an impact on design performance. Foundry fill targets have switched from ensuring a basic minimum density to achieving a maximum density. In addition, density checks for density gradient now require a smooth transition between fill densities in adjacent locations. At 20nm and below, fill requirements must also comply with multi-patterning (MP) restrictions to ensure mask balancing, and designers must begin adding multi-layer fill not just to back-end-of-line (BEOL) metal and via layers, but also to front-end-of-line (FEOL) layers. All of these changing manufacturing requirements impact the complexity of metal fill placement, as well as the number of fill elements in a design.

These changes in fill require sophisticated new fill types and filling strategies. New techniques such as cell-based and multi-patterning-aware fill were integrated into fill engines to provide an automated fill process that can be called from place and route (P&R) tools to ensure an easy-to-use design flow that produces correct-by-construction results. However, the number of fill shapes in advanced node technologies can exceed a billion objects. So an engineering change order (ECO) that arrives late in the tapeout process and requires fill changes in the surrounding area can be a significant engineering challenge. The complexity of replacing fill and reconfirming timing may negatively affect runtime and timing closure, which can lead to a delayed tapeout delivery.

To handle these last-minute design changes, TSMC developed an ECO fill reference flow designed to work in concert with their overall design ECO flow. The TSMC ECO fill flow addresses the same range of fill situations that their full fill flow encounters, but concentrates only on the portion of the design affected by the ECO. This flow can account for the timing impact of fill without slowing down the back-end flow.

The TSMC ECO fill reference flow incorporates Calibre® YieldEnhancer’s SmartFill functionality and Calibre DESIGNrev™ to keep fill shapes in a separate file on disk, similar to the approach that the leading parasitic extraction tools use to
minimize the size of the design database. This proven “merge when needed” approach provides the proper balance between accuracy and performance. The TSMC ECO fill reference flow (shown in the figure to the right) is currently supported for 16nm and 20nm processes. Users can download all the necessary files from TSMC.

By removing and replacing only the fill in the surrounding area, and re-verifying timing only in the affected area, designers can reduce runtime, manage file size, and minimize timing impacts (see the following figure). By restricting the ECO fill operation to only the same locations where actual mask-making changes occur, the TSMC ECO fill reference flow limits the size of the region that must be evaluated for errors, edited, and refilled. This area reduction is accomplished by generating exclude regions, and clipping the fillable database to include only the area around the design ECO.

To reduce the size of the fill database, TSMC uses a cell-based approach to fill the design. If the ECO fill flow does not properly handle fill cells, designers will see an explosion in the fill database. So, to minimize this, Calibre SmartFill only flattens the minimum number of cell instances required to remove existing fill that conflicts with the ECO design shapes. It also removes shapes based only on metal-stack-aware DRC spacings. It then refills only in the areas where ECO changes occurred, rather than refilling the entire chip.

There is a breakeven point in this reference flow—if the area to be refilled is too large, then the efficiencies of scale may be lost. In general, ECO fill strategies are most efficient when the change affects less than 1% of the design area. For bigger changes, the runtime of the ECO fill flow may exceed that of a regular fill run. Generally, good candidates for ECO fill include small areas of change, such as changes in gate functionality that requires a localized rerouting in a limited area. When changes to an entire block indicate that it would be more efficient to simply refill the design from scratch, a hierarchical fill approach may be more appropriate. However, designers must always consider whether minimizing timing impacts and mask costs offset any runtime disadvantage.

This table demonstrates a number of advantages to having a specialized ECO Fill flow that uses the exact same fill deck that was used to fill the design originally.

The results from several real world test cases show that fill runtime was reduced by 34% to 89% by using the ECO fill flow rather than a full refill. In four of the five cases, the number of masks that required changes was reduced, and in one case the ECO fill approach resulted in six fewer masks requiring re-manufacturing. The TSMC ECO Fill reference flow implemented with the SmartFill functionality in Calibre YieldEnhancer provides a push-button solution that can handle any last minute design changes.