TSMC – Page 37 – SemiWiki

October 17, 2014

Recap of the Apple iPad Announcement

Recap of the Apple iPad Announcement
by Daniel Payne on 10-17-2014 at 2:00 pm
Categories: Mobile, TSMC

I watched the live stream product announcements yesterday from Apple and will give you a quick recap of what I gleaned. First off, Apple live stream requires that you use the Safari browser, so that meant that I couldn’t use Google Chrome, so much for adopting web standards.

Apple Products Talked about

iPhone 6 and 6 Plus
This was the biggest and fastest product launch in the history of Apple, which is quite the feat. We’ve been blogging that the A8 SoC used in these products is manufactured byTSMC, using some 2 billion transistors at the 20nm node. The 5.5″ display iPhone 6 Plus now sells about 24% of total iPhone sales, the 4.7″ display iPhone 6 at 62%, and remaining iPhones at 11% (Source: Consumer Intelligence Research Partners). The iPhone 6 starts selling in China today, which is expected to be another growing and emerging market for Apple.

ApplePay
The ApplePay allows for easier purchasing by using the NFC (Near Field Communication) feature in iPhones, and will start in retail stores on Monday. I use NFC and Google Wallet on my Galaxy Note 2, but find that most stores aren’t setup yet for NFC support, so I expect this will be a gradual ramp for ApplyPay as well. Oddly enough my local Best Buy store has NFC-ready checkout, but their software isn’t installed yet so cannot be used. ApplePay will start appearing on web sites as well, competing with the likes of PayPal and Google Pay.

Apple Watch
It’s coming, but you have to wait until early 2015 to buy one. Independent software developers will get an Apple Watch SDK in November, so that will start the race to build new apps that are watch centric.

iOS8, OS X Yosemite
Apple has two operating systems – one for touch devices called iOS8 and the other for mouse-based devices called OS X Yosemite. The latest release of iOS8.1 fixes bugs, adds new features like ApplePay support and is ready on Monday. OS X Yosemite is mostly a cosmetic facelift along with hundreds of incremental improvements, is free, and the 5.1 GB downloads started yesterday. I’ve started using OS X Yosemite on my MacBook Pro and was surprised that during the upgrade the default was set to turn on file encryption, aka FileVault, although I kept it turned off. Mac Mail now also has an annoying bug in it where the From field will occasionally show up with the wrong name in it.

Customer adoption of iOS8 quickly reached 48% of the installed base on iPad and iPhone devices, way ahead of what Android users experience. My iPad 3 and iPad Air are upgraded and working well with iOS8, so far so good.

iPad Air 2, iPad Mini 3
It’s a thinner iPad, slimmed down to just 6.1mm, the world’s thinnest. The display is less reflective, which is a step in the right direction for users that don’t want to look at themselves all day. To me the big news was that this device uses an A8X chip, reported to have 3 billion transistors. We could assume that the manufacturing is TSMC again, because they fabricated the A8 chip, too bad for Samsung this round.

The smaller screen product iPad Mini 3 has the touch ID feature, comes in three colors and is priced from $399 to $599. The Apple marketing folks continue the tradition of offering previous generation iPads at reduced prices, giving consumers multiple price points to choose from.

iMac Retina 5K
Bigger is better when it comes to desktop computing, and the new iMac has a 27″ display with 5K, which is 5,120 x 2,880 pixels. Priced lower than a 4K TV set, this iMac starts at $2,499 and uses the 3.5 GHz quad-core Intel Core i5 chip. We’re still waiting for the day that Apple uses the A-series chips for all of the devices, breaking ties with Intel completely.

Mac Mini
This diminutive Mac Mini box finally got updated with latest Intel processor, faster Thunderbolt 2 ports (20 Gbps speeds) – enabling video streaming to one 4K monitor or dual QHD displays.

Continuity
As you can imagine Apple wants you to own all of their devices, however with two different operating systems how do you share files or apps? They talked a lot about continuity in the latest iOS8 and Mac OS X Yosemite, that now allow you to work between devices on the same app like Keynote. In the demo they started a Keynote presentation on an iPad, then moved over to iMac to continue editing right where they left off, and finally controlled the presentation using Apple Watch and streaming to Apple TV.

Full Disclosure – I own AAPL stock, have Apple products, and use the Samsung Galaxy Note 2.

October 16, 2014

TSMC Breaks More Records in Q3 2014!

TSMC Breaks More Records in Q3 2014!
by Daniel Nenni on 10-16-2014 at 4:00 pm
Categories: Foundries, TSMC

As previously predicted TSMC is having another record breaking SoC quarter. TSMC is my favorite economic bellwether and from what I can see the semiconductor industry will continue to grow this year and next at a rapid rate thanks to TSMC and the fabless semiconductor ecosystem:

We have set a new record of revenue and profitability thanks to strong demand and our successful ramp of 20nm. Our revenue increased 14% sequentially and 29% on a year-over-year basis to reach $209 billionNT. Our gross margin exceeded 50% to reach 50.5% which is also a record since the second half 2006.

20nm is the focus of this quarter and rightly so. Let’s not forget that a famed semiconductor analyst, Dr. Handel Jones of IBS, predicted at the beginning of this year that:

20nm will be a high volume technology node in 2015 but mostly 2016.
16/14nm will provide low cost gates with volume production only in 2017.
10nm will be postponed. Cost per gate will be prohibitive and unclear where demand will come from outside high-speed processors and FPGAs.

Also Read:Handel Jones Predicts Process Roadmap Slips

To be clear, 20nm is in high volume production TODAY and 14nm/16nm will be in high volume production in 2015. In regards to 10nm:

On 10 nanometer development our 10 nanometer development is progressing according to plan. Currently we are working on early customer collaboration for product tape outs in 4Q of 2015. The risk production date remains targeted at the end of 2015. Our goal is to enable our customers’ production in 2016.

To meet this goal we are getting our 10 nanometer design ecosystem ready now. We have completed certification of over 35 EDA tools using ARM CPU core as a vehicle. In addition we have started the IP validation process six months earlier than previous nodes with our IP partners.

TSMC has a dozen 10nm early access customers designing SoCs, baseband/LTE chips, CPUs, GPUs, network processors, FPGAs, and game consoles. So, rather than postponing, TSMC has pulled in 10nm to better align with the Intel 10nm road map. The famed Intel process lead, in regards to SoCs, has slowed since 22nm. The Intel Bay Trail 22nm SoC was released in Q3 2013 while Apple’s 20nm A8 was released in Q3 2014. The Intel 14nm Cherry Trail SoC has now been delayed to Q1 2015 and the Intel 14nm Broxton SoC targeting phones is no longer being discussed publicly.

We are happy to say that 16 nanometer has achieved the best technology maturity at the same corresponding stage as compared to all TSMC’s previous nodes. On the yield the progress is much better than our original plan. This is because the 16 nanometer uses similar process to 20 SoC except for the transistors and since 20 SoC has been in mass production with good yield.

On the performance side compared with the 20 SoC, 16 FinFET is greater than 40% speed, faster than the 20 SoC at the same total power or consume less than 50% power at the same speed. Our data shows that in high-speed application it can run up to 2.3 GHz or on the other hand for low power application it consumes as low as 75 milliwatts per core.

Samsung still seems to have a production lead over TSMC at 14nm. My expectation is that Samsung 14nm SOCs will start revenue in Q2 2015 and TSMC 16nm FF+ SoCs will start in Q3 2015, so Intel’s process lead is narrowing. At 10nm I expect the foundries to be lockstep with Intel (for SoCs). Just my opinion of course.

You can find TSMC quarterly result and presentation materials HERE.

October 11, 2014June 14, 2019

TSMC ♥ Cadence!

TSMC ♥ Cadence!
by Daniel Nenni on 10-11-2014 at 4:30 pm
Categories: Cadence, EDA, IP, TSMC

One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.

Of late, the highest praise has gone to Cadence. I was working in Silicon Valley in the early 1980s when EDA began to flourish. It was mostly DMV (Daisy, Mentor, Valid) when two smaller start-ups merged (ECAD and SDA) in 1988 to create Cadence. I credit Joe Costello with making EDA an exciting place to work. Unfortunately, after Joe left in 1997 Cadence seemed to lose its way. In January 2009 Lip-Bu Tan joined Cadence as President and CEO after serving on the Cadence Board of Directors for five years. To me that was a turning point for Cadence which brought them back to what they are today, an industry leader. Cadence stock agrees as it has more than tripled since Lip-Bu took over as President and CEO.

20nm was a defining node as it required much closer collaboration amongst the fabless semiconductor ecosystem. Double patterning is one example but there are plenty of others. At 16nm we have FinFETs and even more challenges ahead especially for analog and mixed signal design and as we all know Cadence is the AMS design market leader. 10nm is well underway and Cadence is a key player in the development of IP and PDKs to which TSMC acknowledged during their Open Innovation Platform Forum:

Cadence Wins Two TSMC Partner of the Year Awards for Soft IP and 16FF+ Solutions

“We presented the awards to Cadence based on the quality results delivered through its Soft IP and 16FF+ solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence has demonstrated its commitment to working closely with us to bring the highest quality design capabilities to IC designers around the world, and we look forward to continuing our partnership in the years to come.”

Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA, and chief of staff to the CEO at Cadence, commented on the awards, saying, “The award recognition from TSMC reflects our long-standing relationship and further demonstrates our ongoing commitment to delivering a strong IP portfolio and advanced-node technology for next-generation SoC designs.”

Dr. Hsu from Cadence further commented, “Customers that create chips for the world’s newest mobile devices are already tapping into the benefits of the 16FF+ design flows and can start to adopt 10nm FinFET solutions to overcome design complexity and get to market faster.”

This did not come as a surprise to me because of the many EDA people I see in Hsinchu. One of the more critical components of collaboration is the willingness to “show up” and during my travels I most often see Cadence executives. Contrary to unpopular belief, there is no such thing as tossing semiconductor designs over the wall to manufacturing so if you want to know who the key players are in modern semiconductor design and manufacturing spend time at the Hotel Royal, The Sheraton, and the Ambassador Hotel in Hsinchu. Or just hang out in the lobby of TSMC Fab 12.

And yes I know Synopsys and other partners were recognized by TSMC, and rightly so, but I give the SemiWiki award for Most Improved EDA Vendor to Cadence, hands down. Ha ha, you thought I was going to say “absolutely” didn’t you?

More Articles by Daniel Nenni…..

October 4, 2014

The Apple Samsung TSMC Intel 14nm Mashup!

The Apple Samsung TSMC Intel 14nm Mashup!
by Daniel Nenni on 10-04-2014 at 1:00 pm
Categories: Foundries, Intel Foundry, Mobile, TSMC

One of the strengths of the fabless semiconductor ecosystem is competition since it keeps innovation high and prices low. One of the challenges of fostering competition is that you have to make good on a threat of using a competing product during a pricing negotiation. Well, in my opinion, for the next version of the iPhone, Apple did just that. Apple put Samsung and TSMC against each other and as a result will use both Samsung 14nm and the better performing TSMC 16nm FF+ for the 2015 iProducts. Since Samsung is a quarter or two ahead of TSMC on FinFETs, Samsung will get the iPhone business in Q3 2015 and TSMC will get the iPad and maybe a MAC Book in Q4 2015. Qualcomm, NVIDIA, AMD, Broadcom, and the other fabless heavyweights will follow suit. It’s all about wafer price negotiations and that is what keeps us strong.

Also Read:Where will Apple Manufacture the next iPhone Brain?

Common wisdom suggests that Apple would not do business with Intel or Samsung as they both compete with Apple on some level. Samsung aggressively sells competing phones/tablets and Intel gives free SOCs to companies that compete with Apple. But when you are buying billions of dollars of wafers, price tends to trump all. Now let’s talk about the rumors overheard at ARM TechCon last week:

Out of the total volume of A8 chips, Samsung is producing around 30 percent, while TSMC is making 70 percent, sources familiar with the matter said.

The first rumor is that Samsung will get 30-40% of the Apple A8 business. Apple will use the same A8 SoC for the iPhone 6 and iPad products. I’m hoping the A8 will be clocked up for the iPad because I know it can go faster than 1.4GHz! Bottom line: Samsung is NOT supplying 20nm A8 parts to Apple. Show me an iPhone or iPad tear down that proves otherwise and a new iPad is yours. Also according to ZDNet Korea’s Cho Mu-hyun:

Kim Ki-nam, president of the Korean electronic giant’s semiconductor business and head of System LSI business, told reporters at Samsung’s headquarters in Seoul that once the company begins to supply Apple with chips using its latest technology, profits “will improve positively”.

Samsung is expected to start producing application processors (APs) for clients such as Apple, Qualcomm, and AMD, using its 14-nanometre process around the end of the year. Kim declined to comment on when Samsung will start mass producing said chips for clients.

The second rumor is that Samsung won the Apple business for 14nm. As I mentioned above, Apple will use both Samsung and TSMC for the next generation of iProducts in 2015 so this is a half-truth. To me a half-truth is also a half-lie and I have a serious problem with that especially coming from a publicly traded company. Samsung should publicly clarify that it is NOT supplying 20nm wafers to Apple and they are NOT the only vendor supplying Apple FinFET wafers in 2015. Transparency inspires trust, right?

In regards to Intel Custom Foundry, being stuck between Samsung and TSMC in a wafer price war is no way to start your day. Given that TSMC 10nm is on track with Intel Foundry 10nm (remember Intel Foundry has yet to ship production 14nm) and Samsung is a close third, 10nm will be another serious pricing challenge. And let’s not forget that GOLBALFOUNDRIES and IBM are also in the10nm hunt. Competition is for the greater good of the fabless semiconductor ecosystem, absolutely.

More Articles by Daniel Nenni…..

October 2, 2014

ARM ♥ TSMC!

ARM ♥ TSMC!
by Daniel Nenni on 10-02-2014 at 4:00 pm
Categories: Arm, Foundries, IP, TSMC

This week is the 10[SUP]th[/SUP] annual ARM Technical Conference in Silicon Valley. In regards to size, content, and relevance, I believe ARM TechCon is the #1 event for the fabless semiconductor ecosystem for sure. I attended keynotes, sessions, and walked the hallways on Wednesday and Thursday. I wish I could write about everything I learned but I do have NDA issues with my day job and some of the information needs to be verified by other sources before I can post it.

There were Cadence and Synopsys logos all over the place. I saw Aldec, Apache, Ansys, Calypto, Carbon Design, Dorado, Doulos, and Mentor. And not just Mentor, but my favorite EDA CEO Wally Rhines was walking the conference floor as well. You will not find a more “in touch” EDA CEO than Wally. He doesn’t seem to age either so Mentor probably has some cryogenic projects going on up in Wilsonville.

The foundries were well represented by TSMC, GLOBALFOUNDRIES, STMicro, and Samsung. Wait, where was Intel Custom Foundry? Atmel had a very nice IoT exhibit as did Freescale. Xilinx had a great presence as I mentioned HERE. The IP companies were there in force: Arteris, CEVA, Kilopass, Memoir, Rambus, Silicon Image, Sonics, True Circuits, and a few others. All of the EDA and IP companies were announcing support for TSMC 10nm during the conference. Bottom line is that the fabless semiconductor ecosystem gets stronger every year and will continue to do so.

Also Read: TSMC Delivers First FinFET ARM Based SoC!

The big news for me is the ARM/TSMC 10nm roadmap because let’s face it, the majority of the fabless wafers being shipped today include ARM IP. TSMC transformed the semiconductor industry with the pure-play foundry business model and ARM transformed the microprocessor industry with the IP business model so it makes complete sense for these two industry superheroes to team up on 10nm. Notice that the TSMC event was on Monday and Tuesday of this week and ARM TechCon was Wednesday-Friday.

ARM and TSMC Unveil Roadmap for 64-bit ARM-based Processors on 10FinFET Process Technology

“TSMC has continuously been the lead foundry to introduce advanced process technology for ARM-based SoCs,” said Dr. Cliff Hou, TSMC vice president of R&D. “Together with ARM, we proved out in silicon the high performance and low power of the big.LITTLE architecture as implemented in 16FinFET. Given the successful adoption of our previous collaborative efforts, it makes sense that we continue this fruitful partnership with ARM in future 64-bit cores and 10FinFET.”

I talked to Cliff after the TSMC event on Tuesday about the aggressive 10nm schedule (risk production in Q4 2015). Remember, 20nm risk production was in Q4 2013 and 16nm risk production is happening now (Q4 2014). Never before have we seen such a rapid pace of process development. Intel of course shares credit as their “aggressive” marketing tactics motivated the mighty fabless semiconductor ecosystem like never before, ABSOLUTELY!

More Articles by Daniel Nenni…..

ARM TechCon 2014delivers an at-the-forefront comprehensive forum created to ignite the development and optimization of future ARM-based embedded products. By offering three full days of technical tracks, demonstrations, and industry insight from broad and deep levels of industry-leading companies and innovative start-ups, ARM TechCon remains more than a tradeshow; it is a comprehensive learning environment for the entire embedded community, uniting the software and hardware communities.

September 29, 2014August 22, 2024

Who Will Lead at 10nm?

Who Will Lead at 10nm?
by Scotten Jones on 09-29-2014 at 4:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

There has been a lot of discussion on SemiWiki lately around 14nm FinFET technology and who really leads and by how much. I thought it would be interesting to review some process metrics for previous technology generation and then make some forecasts around 10nm.

The focus of this article will be Intel, TSMC and Global Foundries/Samsung as the logic volume leaders:

Intel is the world’s largest semiconductor and far and away the largest IDM logic producer today.
TSMC is the world’s largest foundry
Global Foundries is the world’s second largest foundry. We have combined them with Samsung because they are both members of the common platform alliance and closely aligned in process technology. In fact Global Foundries has licensed Samsung’s 14nm FinFET process technology.

The characterization of process density has shifted over the years and nodes have become less reflective of actual feature sizes and density. A more recent metric that Intel has been using is Gate Pitch (GP) multiplied by Metal 1 Pitch (M1P). This same metric has also shown up in a recent paper by the common platform partners disclosing their 10nm process work. GP x M1P will be the metric used for comparison in this paper.

Intel
The following table presents Intel’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 45nm
| style=”width: 61px; height: 17px” | 32nm
| style=”width: 60px; height: 17px” | 22nm
| style=”width: 60px; height: 17px” | 14nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 319
| style=”width: 60px; height: 17px” | 260
| style=”width: 60px; height: 17px” | 220
| style=”width: 60px; height: 17px” | 180
| style=”width: 61px; height: 17px” | 112.5
| style=”width: 60px; height: 17px” | 90
| style=”width: 60px; height: 17px” | 70
| style=”width: 59px; height: 17px” | 55
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 60px; height: 17px” | 0.85
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 61px; height: 17px” | 0.63
| style=”width: 60px; height: 17px” | 0.80
| style=”width: 60px; height: 17px” | 0.78
| style=”width: 59px; height: 17px” | 0.78
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 350
| style=”width: 60px; height: 18px” | 220
| style=”width: 60px; height: 18px” | 210
| style=”width: 60px; height: 18px” | 160
| style=”width: 61px; height: 18px” | 112.5
| style=”width: 60px; height: 18px” | 90
| style=”width: 60px; height: 18px” | 52
| style=”width: 59px; height: 18px” | 38
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.63
| style=”width: 60px; height: 18px” | 0.95
| style=”width: 60px; height: 18px” | 0.76
| style=”width: 61px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 0.80
| style=”width: 60px; height: 18px” | 0.58
| style=”width: 59px; height: 18px” | 0.74
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 111,650
| style=”width: 60px; height: 18px” | 57,200
| style=”width: 60px; height: 18px” | 46,200
| style=”width: 60px; height: 18px” | 28,800
| style=”width: 61px; height: 18px” | 12,656
| style=”width: 60px; height: 18px” | 8,100
| style=”width: 60px; height: 18px” | 3,640
| style=”width: 59px; height: 18px” | 2,101
|-

All of the pitches down through 14nm are based on Intel public disclosures at IEDM and the IDF. The 10nm forecast is based on applying the average shrink ratio from the previous seven process generations.

TSMC
The following table presents TSMC’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 40nm
| style=”width: 61px; height: 17px” | 28nm
| style=”width: 60px; height: 17px” | 20nm
| style=”width: 60px; height: 17px” | 16nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 310
| style=”width: 60px; height: 17px” | 240
| style=”width: 60px; height: 17px” | 160
| style=”width: 60px; height: 17px” | 162
| style=”width: 61px; height: 17px” | 122
| style=”width: 60px; height: 17px” | 87
| style=”width: 60px; height: 17px” | 90
| style=”width: 59px; height: 17px” | 70
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.77
| style=”width: 60px; height: 17px” | 0.67
| style=”width: 60px; height: 17px” | 1.01
| style=”width: 61px; height: 17px” | 0.75
| style=”width: 60px; height: 17px” | 0.71
| style=”width: 60px; height: 17px” | 1.03
| style=”width: 59px; height: 17px” | 0.78
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 340
| style=”width: 60px; height: 18px” | 240
| style=”width: 60px; height: 18px” | 180
| style=”width: 60px; height: 18px” | 128
| style=”width: 61px; height: 18px” | 95
| style=”width: 60px; height: 18px” | 67
| style=”width: 60px; height: 18px” | 64
| style=”width: 59px; height: 18px” | 46
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.71
| style=”width: 60px; height: 18px” | 0.75
| style=”width: 60px; height: 18px” | 0.71
| style=”width: 61px; height: 18px” | 0.74
| style=”width: 60px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 1.00
| style=”width: 59px; height: 18px” | 0.72
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 105,400
| style=”width: 60px; height: 18px” | 57,600
| style=”width: 60px; height: 18px” | 28,800
| style=”width: 60px; height: 18px” | 20,736
| style=”width: 61px; height: 18px” | 11,590
| style=”width: 60px; height: 18px” | 5,829
| style=”width: 60px; height: 18px” | 5,760
| style=”width: 59px; height: 18px” | 3,220
|-

In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nnm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm.

We have updated this article with actual measured 28nm and 20nm pitch numbers from Chipworks. At 16nm the pitches are based on TSMC’s 2013 IEDM paper. TSMC’s 16nm is reported to have the same metal pitches as their 20nm so we have used the same pitch for 20nm M1. The 16nm gate pitch is larger than our projected gate pitch for 20nm, this is due to the planar to FinFET transition. The 10nm pitches are based on the average TSMC shrink ratios through 20nm. We have excluded 16nm due to the metal pitch pause and planar to FinFET transition.

Global Foundries/Samsung (GF/S)
The following table presents GF/S’s GP, GP shrink ratio, M1P, M1P shrink ration and GP x M1P starting at 130nm and projecting out to 10nm.

[TABLE] border=”1″
|-
| style=”width: 115px; height: 17px” |
| style=”width: 60px; height: 17px” | 130nm
| style=”width: 60px; height: 17px” | 90nm
| style=”width: 60px; height: 17px” | 65nm
| style=”width: 60px; height: 17px” | 40nm
| style=”width: 61px; height: 17px” | 28nm
| style=”width: 60px; height: 17px” | 20nm
| style=”width: 60px; height: 17px” | 14nm
| style=”width: 59px; height: 17px” | 10nm
|-
| style=”width: 115px; height: 17px” | GP
| style=”width: 60px; height: 17px” | 350
| style=”width: 60px; height: 17px” | 245
| style=”width: 60px; height: 17px” | 200
| style=”width: 60px; height: 17px” | 129
| style=”width: 61px; height: 17px” | 90
| style=”width: 60px; height: 17px” | 64
| style=”width: 60px; height: 17px” | 78
| style=”width: 59px; height: 17px” | 64
|-
| style=”width: 115px; height: 17px” | GP shrink
| style=”width: 60px; height: 17px” |
| style=”width: 60px; height: 17px” | 0.70
| style=”width: 60px; height: 17px” | 0.82
| style=”width: 60px; height: 17px” | 0.65
| style=”width: 61px; height: 17px” | 0.70
| style=”width: 60px; height: 17px” | 0.71
| style=”width: 60px; height: 17px” | 1.22
| style=”width: 59px; height: 17px” | 0.82
|-
| style=”width: 115px; height: 18px” | M1P
| style=”width: 60px; height: 18px” | 350
| style=”width: 60px; height: 18px” | 245
| style=”width: 60px; height: 18px” | 180
| style=”width: 60px; height: 18px” | 117
| style=”width: 61px; height: 18px” | 96
| style=”width: 60px; height: 18px” | 64
| style=”width: 60px; height: 18px” | 64
| style=”width: 59px; height: 18px” | 48
|-
| style=”width: 115px; height: 18px” | M1P shrink
| style=”width: 60px; height: 18px” |
| style=”width: 60px; height: 18px” | 0.70
| style=”width: 60px; height: 18px” | 0.73
| style=”width: 60px; height: 18px” | 0.65
| style=”width: 61px; height: 18px” | 0.82
| style=”width: 60px; height: 18px” | 0.67
| style=”width: 60px; height: 18px” | 1.00
| style=”width: 59px; height: 18px” | 0.75
|-
| style=”width: 115px; height: 18px” | GP x M1P
| style=”width: 60px; height: 18px” | 122,500
| style=”width: 60px; height: 18px” | 60,025
| style=”width: 60px; height: 18px” | 36,000
| style=”width: 60px; height: 18px” | 15,093
| style=”width: 61px; height: 18px” | 8,640
| style=”width: 60px; height: 18px” | 4,090
| style=”width: 60px; height: 18px” | 4,992
| style=”width: 59px; height: 18px” | 3,072
|-

We do not have actual pitch numbers for GF/S 20nm technology and we have interpolated them based on available data. At 14nm and 10nm the pitches are based on published values including the 2014 VLSIT 10nm paper from IBM, Samsung, St Micro and Global Foundries.

Density Comparisons
Having reviewed the three companies/groups we can now compare the GP x M1P metric over the range of nodes studied.

[TABLE] border=”1″
|-
| style=”width: 61px; height: 19px” |
| style=”width: 71px; height: 19px” | 130nm
| style=”width: 55px; height: 19px” | 90nm
| style=”width: 58px; height: 19px” | 65nm
| style=”width: 70px; height: 19px” | 45/40nm
| style=”width: 70px; height: 19px” | 32/28nm
| style=”width: 70px; height: 19px” | 22/20nm
| style=”width: 70px; height: 19px” | 16/14nm
| style=”width: 70px; height: 19px” | 10nm
|-
| style=”width: 61px; height: 19px” | Intel
| style=”width: 71px; height: 19px” | 111,650
| style=”width: 55px; height: 19px” | 57,200
| style=”width: 58px; height: 19px” | 46,200
| style=”width: 70px; height: 19px” | 38,800
| style=”width: 70px; height: 19px” | 12,656
| style=”width: 70px; height: 19px” | 8,100
| style=”width: 70px; height: 19px” | 3,640
| style=”width: 70px; height: 19px” | 2,101
|-
| style=”width: 61px; height: 19px” | TSMC
| style=”width: 71px; height: 19px” | 105,400
| style=”width: 55px; height: 19px” | 57,600
| style=”width: 58px; height: 19px” | 28,800
| style=”width: 70px; height: 19px” | 20,736
| style=”width: 70px; height: 19px” | 11,590
| style=”width: 70px; height: 19px” | 5,829
| style=”width: 70px; height: 19px” | 5,760
| style=”width: 70px; height: 19px” | 3,220
|-
| style=”width: 61px; height: 19px” | GF/S
| style=”width: 71px; height: 19px” | 122,500
| style=”width: 55px; height: 19px” | 60,025
| style=”width: 58px; height: 19px” | 36,000
| style=”width: 70px; height: 19px” | 15,093
| style=”width: 70px; height: 19px” | 8,640
| style=”width: 70px; height: 19px” | 4,090
| style=”width: 70px; height: 19px” | 4,992
| style=”width: 70px; height: 19px” | 3,072
|-

This table has been updated since the original post based on measured TSMC 28nm and 20nm pitches from Chipworks. In the table above I have marked in bold the densest process at each node. It is interesting to see that it has moved around from node to node. Based on what has been disclosed to date and reasonable projections it looks like Intel will have the densest process at 16/14nm and 10nm using the GP x M1P metric. Whether this translates into a denser process for actual designs is a different question but GP x M1P is in our opinion a good measure of pure process density.

The same data is also plotted below as the now infamous Intel density comparison:

September 25, 2014

TSMC Delivers First FinFET ARM Based SoC!

TSMC Delivers First FinFET ARM Based SoC!
by Daniel Nenni on 09-25-2014 at 9:00 am
Categories: Foundries, TSMC

Right on cue, TSMC announces 16nm FinFET production silicon. I believe this is the original version of FinFET versus 16FF+ which is due out in 1H 2015. I will confirm this next week at the TSMC OIP event in San Jose, absolutely. Either way this is excellent news for the fabless semiconductor ecosystem and I look forward to the first tear down of a TSMC FinFET SoC in comparison to an Intel FinFET SoC. TSMC 20nm compared quite favorably against Intel 14nm in regards to density and 16FF will do even better.

Let’s not forget that The Chairman (TSMC’s Dr. Morris Chang) speculated that TSMC would not win a majority FinFET market share in 2015. To me this was a head fake to rally the troops. Morris has done this before on conference calls, he is a very clever man. As I mentioned previously, I have never seen TSMC more energized during my last Taiwan trip. Hschinsu on a whole was really buzzing with activity and it was all about FinFETs no matter where I went.

HSINCHU, Taiwan, R.O.C., Sept. 25, 2014 /PRNewswire/ — TSMC (TWSE: 2330, NYSE: TSM) today announced that its collaboration with HiSilicon Technologies Co, Ltd. has successfully produced the foundry segment’s first fully functional ARM-based networking processor with FinFET technology. This milestone is a strong testimonial to deep collaboration between the two companies and TSMC’s commitment to providing industry-leading technology to meet the increasing customer demand for the next generation of high-performance, energy-efficient devices.

For those of you who don’t know, HiSilicon is the ASIC design division of communications giant Huawei. I first encountered HiSilicon in 2008 during an IP licensing negotiation involving SMIC. More recently I visited the new HiSilicon design center in Taiwan. You will be hard pressed to find a leading SoC company without a design center near Hsinchu so they can seamlessly integrate with TSMC. HiSilicon has 100+ people there now and I’m told they are still hiring.

“Our FinFET R&D goes back over a decade and we are pleased to see the tremendous efforts resulted in this achievement,” said TSMC President and Co-CEO, Dr. Mark Liu. “We are confident in our abilities to maximize the technology’s capabilities and bring results that match our long track record of foundry leadership in advanced technology nodes.”

The other interesting thing about this design is that it uses 3D IC packaging combining 28nm mixed signal and 16nm logic chips. TSMC calls this CoWoS (Chip-On-Wafer-On-Substrate) which allows you to integrate multiple chips into a single device. We have written aboutCOWOS many times before and this is an excellent example. To save time and minimize cost you can integrate 28nm blocks with leading edge CPUs for your SoC.

“We are delighted to see TSMC’s FinFET technology and CoWoS[SUP]®[/SUP]solution successfully bringing our innovative designs to working silicon,” said HiSilicon President Teresa He.”This industry’s first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz. This networking processor’s performance increases by three fold compared with its previous generation. Such a highly competitive product can support virtualization, SDN and NFV applications for next-generation base stations, routers and other networking equipment, and meet our time-to-market goals.”

Congratulations to TSMC, HiSilicon, and the entire fabless semiconductor ecosystem for this incredible achievement. And for those who predicted that fabless FinFET chips would “Happen in 2016 at the earliest or never at all”… There are no words left for you.

Also Read: Intel’s 35% Density Advantage Claim Explored

More Articles by Daniel Nenni…..

September 23, 2014

The TSMC iPhone 6!

The TSMC iPhone 6!
by Daniel Nenni on 09-23-2014 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

Fortunately Paul McLellan and I missed IDF. Paul was atop Mt. Kilimanjaro and I was in Taiwan signing books. After reviewing the materials and watching the videos we really didn’t miss much in regards to mobile so no regrets. The Apple event would have been fun even though I won’t be buying an iPhone6 or an iWatch and I will tell you why.

In case you missed it, the first iPhone 6 tear down is up on iFixit and surprise-surprise it is filled with silicon from TSMC’s customers (Apple A8, Qualcomm: modem, PM IC – RF transiever – LTE receive and envelope tracking, Murata wifi module, Broadcom touchscreen controller, NXP NFC, and chips from Skyworks, InvenSense, Avago and TriQuint). The absence of Samsung silicon was not a surprise however and it supports my theory that, given the choice, fabless companies will partner with pure-play over IDM foundries, absolutely. The fact that Samsung and Apple have intellectual property issues and Samsung has constant anti Apple advertisements probably does not help either but that comes with competing with your customers I suppose.

Intel’s 35% Density Advantage Claim Explored

Intel’s 35% Density Advantage Claim Explored
by Daniel Nenni on 09-20-2014 at 1:00 pm
Categories: Foundries, Intel Foundry, TSMC

The previous blog I did on the density difference between Intel 14nm and TSMC 20nm caused quite a stir and many interesting comments which I would like to address. After writing thousands of blogs on a wide variety of topics I have found that playing the devil’s advocate stimulates the most productive conversations and in this case it proved to be true. The Intel Core M vs Apple A8! blog went viral last week and resulted in some very interesting points made in the comment section that I feel should be explored in greater detail.

First is how we measure density. The semiconductor industry is all about packing more transistors in a smaller space. It is part of Moore’s Law, it is how we get less expensive consumer electronics, it is a badge of honor really. There are two transistor numbers you can use: the number of transistors in a design schematic and the number of transistors in the final layout which is then manufactured. The difference between these numbers varies but after taking a quick poll amongst leading edge design and layout people the range is 0-10% more transistors in the layout. Since density is a badge of honor most companies use the layout transistor count but if it serves a marketing purpose they will use the schematic transistor count. Either way, considering the point I’m trying to make, it doesn’t really matter.

Second, comparing the Intel Core M processor and the Apple A8 SoC is like comparing an orange to an apple but this is the only data we have today and it is a good starting point for a density discussion. The architectures are different (CPU vs SoC), the processes are different (20nm planar vs 14nm FinFET), and the companies are very different (IDM versus Fabless).

Third, the performance, power, and functionality of the chips are not part of this discussion. Tear downs and third party benchmarks will be required and they are not available yet. When they are, we can look back on this discussion and see if we were right and if not we can see where we went wrong. All in the interest of science, right?

Here is the argument: Intel claimed a 35% density advantage over TSMC during their November 2103 Investor Meeting using the middle slide above. Intel also used the Altera slide as support for their claim. TSMC rebuffed that claim during a quarterly conference call using the slide on the left.

According to Apple the A8, which is manufactured by TSMC on a 20nm planar process, has about 2B transistors on a 89mm2 die. According to Intel the Core M manufactured on a 14nm FinFET process has about 1.3B transistors on an 82mm2 die.

Given that:

[LIST=1]

According to TSMC, 16nmFF+ has a 15% density advantage over 20nm planar

We do not know what type of transistor count Intel and Apple uses but assume the worst case with a 10% variance (upsize Intel by 10%)

Intel’s 35% density advantage claim just does not hold up, not even close. Time will tell, silicon does not lie, but for now TSMC’s density slide is much more honorable than Intel’s. And let’s not forget that Intel’s processes are highly specialized for a single product and TSMC’s processes serve a much wider range of applications. If true, this lack of density gap is really big news for the fabless semiconductor ecosystem, absolutely!

More Articles by Daniel Nenni…..

September 6, 2014

TSMC OIP: Registration Open

TSMC OIP: Registration Open
by Paul McLellan on 09-06-2014 at 9:00 am
Categories: Foundries, TSMC

It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event. More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

Registration is now open.

The schedule is as follows:

8.00: registration opens
9.00: welcome remarks
9.20: industry overview and corporate updates
9.50: TSMC and the ecosystem for innovation
10.15: feature talk with ARM
10.45: coffee break

Then at 11am the forum splits into 3 parallel tracks: an EDA track, an IP track and an EDA/IP/services track. There will be a break for lunch from 12pm to 1pm. Many of the presentations feature both a design partner of TSMC and an EDA or IP partner. Several of the presentations are on 16FF and 10FF, so this is an opportunity to hear about the experience of TSMC’s partners on the most advanced nodes. In particular, from 4pm until the end of the afternoon on the EDA track Cadence will be talking about various aspects of 16FF and 10FF design. Synopsys and Mentor are also presenting on aspects of 16FF.

The EDA track features presentations from:

AMCC/Cadence
Synopsys (several)
Qualcomm/Mentor
Cadence (several)
Mentor/TSMC
Mediatek/Synopsys

The IP track features presentations from:

Semtech/Snowbush
GUC
ARM
Kilopass
Cadence
CEVA
ARM (several)
Imagination
Synopsys

The EDA/IP/services track features presentations from:

GUC
Lorentz/Altera
eSilicon
Synopsys
Uniquify
Oracle/Mentor
ANSYS (Apache)
Analog bits
M31 Technology
Microchip SSTI

The day concludes with a social hour from 5.30pm to 6.30pm.

If you are doing design with TSMC (and its almost a case of who isn’t?), and especially if you are about to start on a 16FF design, then you should definitely plan to attend. I think the agenda contains a wealth of interesting sounding experience from design groups working right on the bleeding edge.

Full details of the agenda are here. Registration is here.