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TSMC and Flex Logix?

TSMC and Flex Logix?
by Daniel Nenni on 03-26-2016 at 7:00 am
Categories: eFPGA, Events, Flex Logix, IP, TSMC

There was a lot to learn at the TSMC Technical Symposium last week, in the keynotes for sure but also in the halls and exhibits. Tom Dillinger did a nice job covering the keynotes in his posts Key Take aways from the TSMC Technology Symposium Part 1 and Part 2 but there was something interesting that many people may have missed in the exhibit hall.

As you may know this event is invitation only and that includes the companies who exhibit. To exhibit you must have a formal relationship with TSMC and more importantly with TSMC’s top customers so it interesting to see new companies in the exhibit hall and speculate why they are there.

The most interesting new company exhibiting this year in my opinion was Flex Logix Technologies:

FLEX LOGIX ANNOUNCES PROGRAM FOR FAST-TRACK EVALUATION AND PROTOTYPING
Reconfigurable RTL Enables One Design to Serve Varying Customer Requirements

“Architects, front-end designers and physical design teams all need to become familiar with this new technology for applications from MCU to IOT to Networking and more. Like with any technology, it is best to learn by doing and starting simple,” explained Flex Logix CEO and co-founder Geoff Tate. “This new program allows customers to fully evaluate EFLX in detail and in silicon at very low cost.”

Geoff Tate and Andy Jaros manned the booth (Andy and I worked at Virage Logic together years ago). Talking to both the CEO and VP of sales was a great opportunity to understand the Flex Logix value proposition so here it goes:

More and more companies are trying to build flexibility into their SoC designs. The traditional approach has been to overdesign an SoC or functional block to try and anticipate all possible requirements and simply select an option: blow a fuse, spin a metal mask, or make a bond out option to “personalize” a particular chip for a customer or market application.

The theory goes, with advanced process nodes, gates are “cheap”, so this design philosophy is easily justifiable. But what is not cheap are the mask costs not to mention the engineering and validation cost. And there’s the cost of missing a market window if a spec changes or a customer decides they want to tweak a custom built hardware accelerator because their algorithm changed or they want to modify the pinout due to system constraints.

As market requirements and customer demands are changing even more rapidly, designing SoCs with more flexibility in mind is making more and more financial sense. Even if it uses a few more “cheap” gates, can save money on multiple tape outs, and helps keep up with changing requirements.

It requires a slightly different approach to designing chips of course and Flex Logix has the right idea with their Fast Track program to help architects and designers experiment with adding more flexibility to their projects. Additionally, the ability to have one die that can be retargeted to multiple applications improves ROI.

Additionally, the ability to upgrade features in the field, in system, offers the possibility of a new revenue stream: providing optional upgrades that permit better, faster operation. Often the alternative is to fall back to emulation in software which can suck up a lot of processor bandwidth (not to mention power) that can be used elsewhere.

For more detailed information, Don Dingee is our embedded design expert and he has written about Flex Logix twice thus far. Or you can give Andy a ring, he is always good company for a coffee or lunch.

Creating a better embedded FPGA IP product

Reconfigurable redefined with embedded FPGA core IP

FLEX LOGIX, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. The company’s technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex Logix recently secured $7.4 million of venture backed capital. It is headquartered in Mountain View, California and has sales rep offices in China, Europe, Israel, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com

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10nm SRAM Projections – Who will lead

10nm SRAM Projections – Who will lead
by Scotten Jones on 03-25-2016 at 12:00 pm
Categories: Events, Intel Foundry, Samsung Foundry, Semiconductor, TSMC

At ISSCC this year Samsung published a paper entitled “A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization. In the paper Samsung disclosed a high density 6T SRAM cell size of 0.040µm[SUP]2[/SUP]. I thought it would be interesting to take a look at how this cell size stacks up to 6T SRAM cells we have seen to-date and some projections for what other companies 10nm 6T SRAM cell sizes might be.

[TABLE] align=”center” border=”1″
|-
| style=”width: 71px” |
| style=”width: 60px” | 45nm
| style=”width: 60px” | 32nm/
28nm
| style=”width: 66px” | 22nm/
20nm
| style=”width: 66px” | 16nm/
14nm
|-
| style=”width: 71px” | Intel
| style=”width: 60px” | 0.3460
| style=”width: 60px” | 0.1710
(32nm)
| style=”width: 66px” | 0.0920
(22nm)
| style=”width: 66px” | 0.0588
(14nm)
|-
| style=”width: 71px” | Samsung
| style=”width: 60px” | 0.3700
| style=”width: 60px” | 0.1490/
0.1200
| style=”width: 66px” | NA
| style=”width: 66px” | 0.0640
(14nm)
|-
| style=”width: 71px” | TSMC
| style=”width: 60px” | 0.2420
| style=”width: 60px” | 0.1270
(28nm)
| style=”width: 66px” | 0.0810
(20nm)
| style=”width: 66px” | 0.0700
(16nm)
|-

6T SRAM cell size versus node (µm[SUP]2[/SUP]).

Looking at this data you can see that at 45nm and 20nm TSMC led and at 28nm Samsung led (the leaders at each node are in bold). At 16nm TSMC chose to take a conservative approach and leverage their 20nm process pitches for their first FinFET resulting in a larger SRAM cell size than would otherwise have been expected. Intel very aggressively scaled their process and took the lead.

I have taken 6T SRAM cell size data for Intel back to 130nm, Samsung back to 90nm and TSMC back to 130nm and plotted SRAM cell size versus node. Using a power law to fit the curves the R[SUP]2[/SUP] values are >0.98 for Intel and TSMC and >0.97 for Samsung clearly indicating a very good fit. Using the resulting equations, I have projected Intel and TSMC 10nm 6T SRAM cell sizes. For Intel I project a 6T SRAM cell of 0.0284µm[SUP]2[/SUP] and for TSMC of 0.0238µm[SUP]2[/SUP].

Assuming TSMC returns to their historical SRAM trends they will once again have the smallest SRAM cell size. This may be optimistic because Intel is expected to have a smaller contacted gate pitch and minimum metal pitch than TSMC at 10nm. In fact, we expect TSMC’s 7nm process to have similar pitches to Intel’s 10nm process. We should note here that TSMC is expected to begin ramping 10nm at the end of 2016 and they are targeting the end of 2017 for a 7nm ramp. With Intel delaying 10nm to 2017 TSMC’s 7nm and Intel’s 10nm may be ramping around the same time.

The bottom line is based on my analysis the Samsung 10nm 6T SRAM cell size looks significantly larger than what I would expect from Intel and TSMC.

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Key Takeaways from the TSMC Technology Symposium Part 2

Key Takeaways from the TSMC Technology Symposium Part 2
by Tom Dillinger on 03-22-2016 at 4:00 pm
Categories: Events, Semiconductor, TSMC

In Part 1, we reviewed four of the highlights of the recent TSMC Technology Symposium in San Jose. This article details the “Final Four” key takeaways from the TSMC presentations, and includes a few comments about the advanced technology research that TSMC is conducting.
Continue reading “Key Takeaways from the TSMC Technology Symposium Part 2”

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Key Takeaways from the TSMC Technology Symposium Part 1

Key Takeaways from the TSMC Technology Symposium Part 1
by Tom Dillinger on 03-20-2016 at 7:00 am
Categories: Automotive, Events, FinFET, IoT, Mobile, Semiconductor, TSMC

TSMC recently held their annual Technology Symposium in San Jose, a full-day event with a detailed review of their semiconductor process and packaging technology roadmap, and (risk and high-volume manufacturing) production schedules.
Continue reading “Key Takeaways from the TSMC Technology Symposium Part 1”

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TSMC and ARM Serving up 7nm!

TSMC and ARM Serving up 7nm!
by Daniel Nenni on 03-15-2016 at 10:00 am
Categories: Arm, IP, Semiconductor, TSMC

One thing I learned while writing the books about TSMC and ARM is that collaboration has always been at the core of both companies. They started with collaboration on day one and it is now a natural part of their business models. And the word collaboration in the fabless semiconductor ecosystem gets redefined at every process node, absolutely.

As I write this I am in the lobby of the Hilton at the San Jose Convention Center waiting for the 22[SUP]nd[/SUP] annual TSMC Technical Symposium to start. This event is unique as it is invitation only for TSMC collaboraters (customers and partners). The Toms (Tom Simon and Tom Dillinger) and I will be covering it live for SemiWiki so stay tuned.

One of the more interesting press releases to come out before the event is the one highlighting the TSMC and ARM collaboration on 7nm. Interesting because it focuses on the server market (high-performance compute) which should be a very big swing for the fabless semiconductor ecosystem.

The first book we published was a brief history of the fabless semiconductor ecosystem. I really have to thank Intel for the motivation on that book. Remember when Mark Bohr of Intel said, “The fabless model is collapsing”? This was back in 2012 and referenced TSMC 20nm. Today TSMC will talk about 16FFC, 10nm, and 7nm, all of which will signal for the first time a process lead change from IDM to foundry. So not only was the fabless business model NOT collapsing, it is now challenging the feasibility of the IDM model.

The second book we published is a detailed history of ARM followed by brief histories of Apple, Samsung, and Qualcom. This is an SoC focused book documenting the billions of ARM enabled devices. In the epilogue we talk about how ARM gets to the trillions of devices and that of course brings us to IoT, which is what our third book is about.

Will there be a fourth SemiWiki book? Well, we are looking for topics right now with the leading candidate being the server market and this is why:

“Existing ARM-based platforms have been shown to deliver an increase of up to 10x in compute density for specific data center workloads,” said Pete Hutton, executive vice president and president of product groups, ARM. “Future ARM technology designed specifically for data centers and network infrastructure and optimized for TSMC 7nm FinFET will enable our mutual customers to scale the industry’s lowest-power architecture across all performance points.”

“TSMC continuously invests in advanced process technology to support our customer’s success,” said Dr. Cliff Hou, vice president, R&D, TSMC. “With our 7nm FinFET, we have expanded our Process and Ecosystem solutions from mobile to high performance compute. Customers designing their next generation high-performance computing SoCs will benefit from TSMC’s industry-leading 7nm FinFET, which will deliver more performance improvement at the same power or lower power at the same performance as compared to our 10nm FinFET process node. Jointly optimized ARM and TSMC solutions will enable our customers to deliver disruptive, first-to-market products.”

Now that the foundries have the process lead and 64-bit ARM technology has a significant price/power/performance advantage over other architectures, I see the sever market as being the next big Fabless v. IDM battlefield. Remember, at the 2015 ARM TechCon it was stated that ARM is predicting a 25% server market share by 2020. SemiWiki is totally on board with this strategy and, if successful, it will certainly make a good book.

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TSMC 2016 Technology Symposium and Apple SoCs!

TSMC 2016 Technology Symposium and Apple SoCs!
by Daniel Nenni on 03-08-2016 at 4:00 pm
Categories: Events, FinFET, Semiconductor, TSMC

It is that time again, time for the originators of the pure-play foundry business to update their top customers and partners on the latest process technology developments and schedules. More specifically, all of the TSMC FinFET processes (16nm, 10nm, 7nm, and beyond), TSMC IP portfolio (CMOS image sensor, Embedded Flash, Power IC, and MEMS), TSMC’s backend technology (InFO and CoWos), and the latest update on the TSMC OIP Ecosystem.

The future of the semiconductor industry is promising with many growth opportunities ahead. To capture these opportunities, we need to continue to work as a collaborative innovation force. Together, we will help each other grow business and stay competitive. This vision is the foundation for the TSMC Grand Alliance. At TSMC, customers are always at the center of all our efforts. With this spirit, TSMC has become our customers’ TRUSTED technology and capacity provider along the way.

It will be interesting to hear more about TSMC’s FinFET market share and if they really did double down on 16nm capacity. I would also like to know where 10nm stands. In my opinion it will be a quick transition node like 20nm that most companies (except for Apple) will skip so they can stay on the new and improved 16FFC until 7nm goes into production. My guess is that TSMC will spend much more time on 7nm than 10nm next week. It will also be fun to try and figure out what Apple is up to based on TSMC’s updates. For example this comment from the last conference call tells me that Apple will be using a 16nm FFC variant for the iPhone 7 this fall:

As customer accelerated their technology migration into 16-nanometer node, we anticipate a significant demand drop in 20-nanometer in 2016. However, we also expect a continual ramp-up of 16-nanometer this year and expect it to contribute more than 20% of wafer revenue in 2016. We estimate our foundry market segment share of 16, 14-nanometer node increases from about 40% in 2015 to above 70% in 2016 exceeding the previous prediction we made in mid-2014.

The other Apple “tell” is the InFO packaging technology. Last year TSMC predicted that InFO will contribute more than $100 million in revenue by Q4 2016. If you consider packaging is $2 or so per chip in revenue contribution that is a SIGNIFICANT amount of chip volume which again points to Apple using TSMC for the A10 SoC.

There are four different TSMC Technical Symposiums in the U.S. and others around the world after these:

Tuesday, March 15
San Jose McEnery Convention Center
San Jose, CA
Registration Opens at 8:30 a.m.

Tuesday, March 22Boston Marriott Burlington
Burlington, MA
Registration Opens at 8:30 a.m

Thursday, March 24
Four Seasons, Austin
Austin, TX
Registration Opens at 8:30 a.m.

If you are not one of the lucky golden ticket holders, Tom Simon and I will be there and will post our observations and opinions on SemiWiki shortly thereafter. If you are looking for specific information let us know in the comments section and we will do our best to get it.

Established in 1987, TSMC is the world’s first dedicated semiconductor foundry. As the founder and a leader of the Dedicated IC Foundry segment, TSMC has built its reputation by offering advanced and “More-than-Moore” wafer production processes and unparalleled manufacturing efficiency. From its inception, TSMC has consistently offered the foundry segment’s leading technologies and TSMC COMPATIBLE® design services.

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FinFET For Next-Gen Mobile and High-Performance Computing!

FinFET For Next-Gen Mobile and High-Performance Computing!
by Daniel Nenni on 02-22-2016 at 7:00 am
Categories: FinFET, Mobile, Semiconductor, TSMC

Evolving opportunities call for new and improved solutions to handle data, bandwidth and power. Moving forward, what will be the high-growth applications that drive product and technology innovation? The CAGRs for smartphone and data center continue to be very strong and healthy.
Continue reading “FinFET For Next-Gen Mobile and High-Performance Computing!”

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Double Digit Growth and 10nm for TSMC in 2016!

Double Digit Growth and 10nm for TSMC in 2016!
by Daniel Nenni on 12-05-2015 at 12:00 pm
Categories: Semiconductor, TSMC

Exciting times in Taiwan last week… I met with people from the Taiwanese version of Wall Street. They mostly cover the local semiconductor scene but since that includes TSMC and Mediatek they are interested in the global semiconductor market as well. They also have an insider’s view of the China semiconductor industry which is very complicated.

The big news of course is that TSMC is predicting double digit revenue growth and 10nm is on schedule for production in 2016. What that really means is that Apple will use TSMC 16FFC exclusively for the A10 (iPhone 7) and 10nm will be ready for the A10x. Morris Chang of course predicted this last year when he said TSMC would regain FinFET market leadership in 2016. This also means that TSMC will officially have the process lead in 2016 since Intel has pushed out 10nm until 2017. So congratulations to the hard working people at TSMC, absolutely!

The other big news is that 7nm is also on track. It will be déjà vu 20nm to 16nm for TSMC where 10nm will be a very quick transitional node right into 7nm. 20nm and 16nm used the same fabs which is why 16nm ramped very quickly, one year after 20nm. 10nm and 7nm will also share the same fabs so yes we will see 7nm in 2017 and that means TSMC 7nm will again have the process lead over Intel 10nm. Exciting times for the fabless semiconductor ecosystem!

Given the quick transition of 10nm to 7nm, quite a few companies will skip 10nm and go right to 7nm. Xilinx has already publicly stated this, I’m sure there will be more to follow. SoC companies like Apple, QCOM, and Mediatek that do major product releases every year will certainly use 10nm. I would guess AMD will use 10nm as well to get a jump on Intel. That would really be interesting if AMD released 10nm and 7nm CPUs before Intel. The server market would certainly welcome the competition.

The other interesting news is that Chipworks confirmed that the A9x in the iPad Pro is manufactured using TSMC 16FF+. I have read the reviews of the iPad Pro and have found them quite funny. One very young “Senior Editor” from Engadget, who has zero semiconductor experience and doesn’t even own an iPad Pro, made this ridiculous statement:

“It’s often vaunted that ARM-based chips are more power efficient than those based on Intel’s x86. That’s just not true. ARM and x86 are simply instruction sets (RISC and CISC, respectively). There’s nothing about either set that makes one or the other more efficient.”

I brought my iPad Pro with me to Taiwan and must say it is a very nice tablet. When it first arrived I was a little shocked at how big it actually was but the performance, display, and battery life is absolutely fabulous! I’m comparing it to a Dell Core i7 based laptop and an iPad 2 of course so the bar is pretty low. But it also runs circles around my iPhone 6. Given the size of the A9x (147mm) versus the A8x (128mm) I’m wondering if it will be used for the next iPad Air. If so, that would be the tablet of the year for sure.

And can you believe our own Oakland Warriors are 20-0 to start the season which is an NBA record!?!?!?!? GO WARRIORS!!!!!

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When Talking About IoT, Don’t Forget Memory

When Talking About IoT, Don’t Forget Memory
by Tom Simon on 11-13-2015 at 7:00 am
Categories: IP, Semiconductor, TSMC

Memory is a big enough topic that it has its own conference, Memcon, which recently took place in October. While I was there covering the event for SemiWiki.com I went to the TSMC talk on memory technologies for the IoT market. Tom Quan, Director of the Open Innovation Platform (OIP) at TSMC was giving the talk. IoT definitely has special needs for memory because of the need for low power, data persistence and security.

Tom Quan started the talk with an informative view of the IoT market. I have heard a lot of IoT overviews, but I listed with a keen ear to learn how TSMC views this market. Since 1991 there have been three big growth drivers for the semiconductor industry. IoT promises to be the fourth.

The first was personal computing which saw 7X growth from 1991 to 2000. Next came mobile handsets demonstrating 9X growth from 1997 to 2007. Last we have smart mobile computing, which lumps together mobile computing, internet, mobile communications, and sensing. This segment grew by 12X from 2007 to 2014. Clearly the IoT is the next big thing and will likely continue this accelerating this trend. The conclusion is that IoT will be the next big growth driver for the semiconductor industry. The sum of PC’s smartphones, tablets and IoT is expected to approach 20 billion units by 2018, compared to roughly 8 billion total today. The last year there is hard data was 2013 with ~5 billion units.


IoT is really an extension of mobile computing. Tom’s talk broke it down into the four umbrella categories of smart wearables, smart cars, smart home and smart city. It will consist of smart devices on smart things. Think of health sensors, gesture and proximity, chemical sensors, positional sensors and more. So where do today’s technologies stand as far as meeting the requirements of the IoT?

Probably every metric for design will be stressed by IoT. Unit volumes will go from the single-digit billions of the PC era to hundreds of billions in the IoT era ahead. Operating times for devices will need to go from hours to years. This in turn demands that the hundreds of watts that PC’s used transform into nano watts for edge sensors and the like. Additionally, new technologies, materials and architectures will need to be developed.

To make these transitions everything will need to be moved forward technologically. The slide below shows how this might work for the wearables segment


A huge part of this will involve embedded memory. Right now SRAM is used primarily for volatile memory. There are a number of solutions for non-volatile memory (NVM), including several future technologies that are very promising. The two major axes for NVM are density (size) and endurance (re-writability). Small sizes that do not need high endurance are things like configuration bits, analog trim info, and calibration data. The work well with one time programmable (OTP) approaches.

Even some boot code can be stored in OTP when it is configured to simulate re-writable memory. However, the number of re-writes will be limited as the non-reusable bit cells are utilized.

Flash and eeprom are good for applications that require larger sizes and more re-write endurance. But they come with the penalty of requiring additional layers or special processes.

Tom suggested that magneto-resistive RAM (MRAM) is one technology that shows some promise. It harkens back to the old core memories, but is scaled to nanometer size. Of the two original approaches for MRAM only the spin-transfer torque (STT) technology has been proven to scale well. There are two competing approaches for this: In-Plane and Perpendicular. MRAM using STT is very fast and uses low power. So it looks very promising as a NVM replacement that can also be used for SRAM replacement.

Another area of promise for future NVM solutions is resistive RAM or RRAM which uses the memristor effect in solid state dielectrics. There are several flavors of this technology being researched. But RRAM is not as far along commercially as MRAM is. However, this is an active area of research and the frequently use high-k dielectric HfO2 material has been discovered to work as RRAM.

Advances in NVM will have a huge impact on IoT. Power savings from having readily available persistent storage will open up new application areas. Think of not having to save system RAM when entering sleep. To further save power TSMC continues to add ultra low power processes to its existing process nodes. IoT will be driven in large part by technologies that allow edge node devices to be power sipping.

For more info on TSMC’s Open Innovation Platform look here.