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Intel
Posted on by Claudio Avi Chami

Intel Altera FPGA at the heart of an autonomous Audi A8

Intel Altera FPGA at the heart of an autonomous Audi A8
by Claudio Avi Chami on 10-02-2016 at 4:00 pm
Categories: Automotive, Foundries, FPGA, Intel

Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech. The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone V FPGA which provides sensor fusion, combining data from multiple sensors in the vehicle for highly reliable object detection and Deterministic Ethernet communications used to transport high bandwidth data within the vehicle.

The zFAS board receives and processes data from:

  • Ultrasonic sensors around the car
  • Front and rear radars
  • Top view camera
  • Front laser scanner
  • Wide angle front camera

The board has also actuators to control:

  • Steering wheel
  • Gear
  • Accelerator
  • Etc.

On ASDF-2015 (Altera SoC Developer Forum, now renamed ISDF since Altera was acquired by Intel), TTTech commented on various aspects of the Piloted Driving technology that would be available to the public during 2017.

Importance of Autonomous Driving

Autonomous driving will:

  • Improve safety – sensor information and processing could avoid up to 40% of today’s accidents
  • Liberate the driver from monotonous driving, i.e. commuting during rush hours
  • Provide new ways of mobility for people that cannot drive, deliveries, car pools, etc.

Key Technical aspects

The Piloted Driving must provide:

  • Fail-safe operation – Even if the system is an assistant, it cannot be guaranteed that the human driver can take control immediately. Upon a single component failure, the system must still be able to take the car to a secure stop.
  • Integration of safety devices with high performance devices. Processing devices share a Gigabit Ethernet backbone with real time messaging capabilities (TSN – Time Sensitive Network).
  • SW integration of applications and the operating systems running at the diverse platforms.
  • Fast deployment by usage of readily available Altera IPs and custom IPs.

Additional information:
TTTech announcement
Altera press release
Audi details piloted driving technology

My blog: FPGA Site

Other entries from me:
Soc FPGA for IoT Edge Computing
FPGAs at Deep Machine Learning

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