GlobalFoundries 22nm FD-SOI: What Happens When

Earlier in the week I wrote about GlobalFoundries announcement of 22nm FD-SOI. At SEMICON West there were three events that filled in some more details. First, on Tuesday, a lunch presentation given by SOITEC who make the wafer blanks that FD-SOI requires. Then on Wednesday I sat down for an hour with Gary Patton and Subi Kengeri to get more details. And finally, on Wednesday evening there was a meeting with many of the people who are participating in the 22nm FD-SOI ecosystem. See also GlobalFoundries FD-SOI. Yes, it’s trueGary Patton used to be the head of R&D at IBM Semiconductor. Since IBM is retaining semiconductor R&D then he was what was called a “voluntary” and he could decide whether to remain with IBM or join GlobalFoundries. He decided to join GF as the CTO and says he is “all in”. He is impressed with Sanjay Jha (who I assume was also the person who closed the deal with Gary to bring him over). A bit of history. IBM used SOI for its high end processors, but not fully-depleted, partially-depleted. That is a process that is very high performance, but expensive, and hard to deal with. There is also an RF-SOI process used by both IBM and GlobalFoundries (in Singapore). This has become the substrate of choice for building radios in the modern era with multiband phone. Your phone has some in since 100% of phones do these days (it is a lot cheaper to manufacture than SiGe or GaAs). The IBM RF process (where they are world leaders) will run in Burlington, Dresden and Singapore. See also GlobalFoundries Adds RF to 28nm Gary said that despite deciding to primarily go forward with FinFET that IBM continued to do research on FD-SOI at Albany. Plus, of course, STMicroelectronics developed 28nm FD-SOI which GlobalFoundries licensed. But when they went to customers, they were told the performance wasn’t high enough. So they decided to develop a 22nm version with the aim of getting very close to FinFET performance but with a manufacturing cost the same as 28nm, and much lower power. As I said in my earlier blog, there are actually 4 different processes that make up the 22FDX process family although it is very modular. Each process has a couple of extra masks but it is almost the same basic process. Why did they do this? After all, GlobalFoundries already has 14nm FinFET (licensed from Samsung). The business driver is that volume and growth are both higher at the low end. Yes, the most advanced application processors for mobile need FinFET but the price is too high for the mainstream. Think of a cheap application processor with battery life of a week for emerging markets. So what are the key features:

• operation as low as 0.4V. It is the only process in the world that can do this, including any that are known to be in development
• integrated RF. The insulating substrate makes this a lot easier
• body bias allowing for tradeoffs between power and performance under software control
• up to 70% lower power than 28HKMG
• performance up to 70% faster than 28HKMG (with FBB at 1.5V, can actually go to 1.8V) although not at the same time as the lowest power
• 50% fewer immersion layers than FinFET (hence the significantly manufacturing cost and lower mask cost)
• 20% smaller die than 28 planar

So what about availability? The initial PDKs exist and have gone to early customers and IP developers. Because 22FDX is similar to 28nm FD-SOI, doesn’t require double patterning, and doesn’t have the complexity of FinFET, the program is on an accelerated schedule with design enablement (EDA, IP etc) working in parallel with technology development. They expect early tapeouts soon after the technology is qualified. So when will that be? They are running internal shuttles already (they call them TQE). They will start external shuttles in Q1 of 2016. Risk production is planned for the end of 2016. Apparently the first silicon run of the “lightning” testchip was closer to the target than anyone had ever seen before, with N transistors on the dot and P just 2% off. The process will run in the Dresden fab (where Dan has been this week, along with CEO Sanjay Jha, not to mention Angela Merkel). It uses the same toolset as 28nm. It could also run in Malta or East Fishkill, but not Singapore. There is plenty of capacity for high volume customers. I asked Gary about 10nm and 7nm. He pointed out that with the IBM semiconductor acquisition that there is a huge infusion of talent who have done leading edge TD for decades. Most of them are now in Malta to accelerate 10/7nm plus there is the Albany Nanotech Center just 20 minutes away. Later in the evening there was a one hour panel session, moderated by Subi, with:

• Marie-Noëlle Semeria, CEO, Leti (research on FD-SOI)
• Paul Boudr​e, CEO, Soitec (manufacturer of base wafers)
• Ron Moore, VP Marketing, ARM (physical libraries and microprocessors)
• Juan Rey, Senior Engineering Director, Mentor Graphics (EDA)
• Brandon Wang, Group Director, Strategic Programs, Cadence (EDA and IP)
• Jamil Kawa, Group Director, Synopsys (EDA and IP)
• Bill Wang, VP and GM, VeriSilicon Holdings (design services)
• Patrick Soheili, VP, Product Management and Corporate Development, eSilicon (fabless ASIC)
• Dasaradha Gude, CEO, INVECAS (design services)

I won’t go into what everyone said. The main conclusions were that the forward body bias (FBB) is the only thing that requires special attention. Obviously physical verification rule decks need to be created but since DRC/LVS already supports 20nm planar, 16nm FinFET, 28FD-SOI, no issues are anticipated. The IP people all had 28FD-SOI experience and also don’t expect any issues. Ron Moore of ARM confirmed that they had PDKs and they were investigating the performance of ARM processors (which also means they must have built a preliminary standard cell library). So, it’s been FD-SOI week all week. Given everything I’ve seen and heard this is a real announcement of something significant.