Common Platform: Onward to the Future

There were keynotes from all three semiconductor partners in the Common Platform Alliance and, as if to show how common they are, they all talked about the problems that need to be addressed in the next decade and a half and they all said pretty much the same thing. Gary Patton of IBM went first and so he got to say everything first. Plus, it is clear, IBM does all the early research before technologies reach the point at which cooperative development can begin.

Gary started off by pointing out technology shifts seem to last about a decade before a new disruptive change is required. They used to build servers out of bipolar in the 1980s until the heat limits meant that they switched to planar CMOS in the 1990s. Various changes such as high-K metal gate and embedded high performance memory extended this. In 2010 things go 3D, at both the big and small level. Small, in the switch to FinFETs, and large in the sense of stacking die using TSV technology. These should last until about 2020 or so when new technology will be needed based on silicon and carbon nanotubes and integrated photonics.

For the time being, IBM is mostly focused on SOI with up to 15 levels of metal for servers. Samsung and GF are mainly focused on bulk for the SoC business, especially mobile.

The challenge to get down to about 10nm fall into 4 areas:

• lithography
• devices
• interconnect
• packaging and subsystem integration

In litho, we are having to switch to double patterning (which, of course, takes twice as long). But the lithography is now so complex it is no longer possible to stick with restrictive design rules (don’t do this and your chip will work) and instead there is a switch to prescriptive design rules (these are the only patterns that you are allowed).

EUV is coming at some point but there are still major challenges. The biggest, of course, is that you can’t build lenses so there is the switch to reflective optics. One thing I hadn’t realized is that this means that your mask can’t have a pellicule to keep defects out of the optical plane, which is another challenge. That’s on top of the changes: new photoresist, new mask material, new wavelength of light and so on. EVU is currently at around 5-10 wafers per hour and needs to get up to over 100 to be economically viable.

For devices, as probably everyone knows, we will switch to fully depleted FinFETs in the short term. Further out we will want to switch to carbon electronics which has very high carrier mobility. But manufacturing is a big challenge since carbon nanotubes don’t always form properly as semiconductors and sometimes simply form as metallic conductors.

Interconnect is a major challenge since nothing good comes out of scaling: resistance goes up, capacitance goes up, reliability gets worse, insulator reliability gets worse. One promising area is integrated photonics, where multiple signals (wavelengths) can be propagated down the same waveguide and then multiplexed out. Otherwise it is basic incremental process improvement, slightly better materials and so forth.

The challenge in packaging is firstly power and thermal, getting the heat out. But there are also issues as die get more fragile and packages get less rigid leading to reliability issues. And all the time it is necessary to boost the bandwidth between the chip and its environment using finer pitches and improved contacts. One thing I hadn’t realized is that the switch to lead-free means stiffer contact between the chip and the package, again a reliability issue.

At the lunch, GF said that 32nm is in production with real product in the line (IBM confirmed this saying they are running 32nm SOI at GF). The yield issues seem to be solved with yields doubling in a quarter. 28nm is in early production with real products in the line. 20nm risk production for LPE will be this year and for LPM next year.