Power-SOI: The Reliability Engine Behind Functional Safety ICsPower-SOI technology is rapidly emerging as a foundational…Read More
ASML High-NA EUV is Not Ready for High-Volume ProductionContrary to the popular press, ASML High-NA EUV…Read More
What Winemakers and Chip Designers Have in CommonConsider this a standout presentation at the Silicon…Read More
Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them ConsistentAccurate, complete, and consistent technical documentation is a…Read More
John Cooley has an interesting “scoop” on the Synopsys-EVE acquisition. The acquisition itself is not a surprise, it is the one big hole in Synopsys’s product line and EVE is the perfect plug to fill it. It was also about the only thing Cadence has (apart from PCB) that Synopsys does not.
The interesting thing … Read More
With an estimated 7 billion connected devices, the demand for rich content, including video, games, and mobile apps is skyrocketing. Service providers around the globe are scrambling to transform their networks to satisfy the overwhelming demand for content bandwidth. Over the next few years, they will be looking to network… Read More
Much has been written about the new iPhone 5 and iOS 6 in terms of the features, specifications, bill of materials, and chips used in the design. Today I’ll share my experiences of actually using the new iOS 6 on iPad as an EDA blogger.
Upgrading to iOS6
Clicking the On button and noticing that the App Store icon has something new,… Read More
Most companies in the memory business have ReRAM on their radar if not their roadmaps. Toshiba have made some bullish comments about the roadmap and chip size for ReRAM at a recent R&D Strategies Update. At face value, the schedule would put Toshiba quite a bit ahead of their competitors. Over at ReRAM-Forum.com, we have done… Read More
When I worked for VaST we went to a show that I’d never heard of in EDA: SAE Convergence (SAE is the Society of Automotive Engineers). It is held once every two years and it focuses on transportation electronics, primarily automotive although there did seem to be some aerospace stuff there too. This is an even year, Convergence… Read More
I’ve been digging around the Interwebs a bit trying to find out what the received wisdom is about how big a cost reduction can be expected if and when we transition to 450mm (18″) wafers from today’s standard of 300mm (12″). And the answers are totally all over the place. They vary from about a 30% cost reduction… Read More
RTL is an acronym for Register Transfer Level and refers to a level of hardware design abstraction using Registers and logic gates. Here’s an example schematic showing one DFF as a register, and one inverter as a logic gate.
Figure 1: RTL diagram of a DFF (D Flip Flop) and Inverter… Read More
At DAC 2012 GLOBALFOUNDRIES and Solido presented a user track poster titled “Understanding and Designing for Variation in GLOBALFOUNDRIES 28-nm Technology” (as was previously announced here). This post describes the work that we presented.
We set out to better understand the effects of variation on design at 28-nm. In particular,… Read More
An empty Fab is a terrible thing to waste, especially when it is leading edge. By the end of the year Intel will, by my back of the envelope calculation, be sitting with the equivalent of one idle 22nm Fab (cost $5B). What would you do if you were Paul Otellini?
Across the valley, in Cupertino, you have Tim Cook, whose modus operandi is … Read More
For all the raving and ranting and hand-wringing about the iPhone 5, the centerpiece of the device – the new A6 SoC – is proving to be a marvelous piece of engineering.… Read More
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SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability