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T’is the season for…semiconductor forecasts

T’is the season for…semiconductor forecasts
by Paul McLellan on 12-20-2011 at 3:10 pm

T’is the season to be jolly…and to predict the next year’s semiconductor market.

KPMG does a regular survey of senior executives in semiconductor companies to get their outlook on the year ahead. The message this year is mixed. 41% of executives expected their business to grow by more than 5% next year, which sounds not too bad until… Read More


View from the top: Chris Rowen

View from the top: Chris Rowen
by Paul McLellan on 12-20-2011 at 1:41 pm

I met with Chris Rowen, CEO of Tensilica, last week to get his outlook on the year ahead.

He gave me an interesting quote from his time at Silicon Graphics. “We wanted to be very fast in development not to be first to market but so that we could be the last to start.”

A lot of what Tensilica does is bound up with evolving standards in audio,… Read More


Why AMD is Up Q4, While Intel is Down

Why AMD is Up Q4, While Intel is Down
by Ed McKernan on 12-19-2011 at 5:45 pm

Immediately following Intel’s announcement that they expected Q4 revenue to come up short by $1B, Rory Read the new CEO of AMD, countered that they were on track to meet their original guidance (see article). Furthermore, “In 1Q and 2Q, maybe you see some manifestations, but I wouldn’t bet against the supply chain,”… Read More


What Will 2012 Bring The Semiconductor Ecosystem?

What Will 2012 Bring The Semiconductor Ecosystem?
by Daniel Nenni on 12-18-2011 at 4:30 pm

During my annual holiday meal with one of my favorite EDA icons some rather bold predictions were made. On his side it was more of what he would LIKE to see happen, on my side it was more of what will HAVE to happen for the semiconductor ecosystem to thrive in the coming years.

Mike Gianfagna (Viva Italia!) spent 15+ years with RCA/GE Semiconductor… Read More


Will Rising Smartphone Tide Lift Semiconductor Boats in 2012?

Will Rising Smartphone Tide Lift Semiconductor Boats in 2012?
by Ed McKernan on 12-16-2011 at 5:12 pm

Memo to Self: When all else fails, return to the Smartphone Market!

The announcement by Intel earlier this week that they would come up short this quarter is a reminder that it is not growth, but very high growth that covers a Multitude of Economic Sins (many which are unforeseen). The semiconductor industry has had to endure three… Read More


Clock Design for SOCs with Lower Power and Better Specs

Clock Design for SOCs with Lower Power and Better Specs
by Daniel Payne on 12-15-2011 at 5:03 pm

Dan Ganousis posted in our SemiWiki forums about a newer technique to lower the power consumed by GHz clocks on SOC designs and asked if I was interested to learn more, so we met today via WebEx. Dan is with a company called Cyclos Semiconductor, co-founded in 2006 by Marios Papaefthymiou, President and Alexander Ishii, VP of Engineering.… Read More


IC capacity utilization declined in 3Q 2011

IC capacity utilization declined in 3Q 2011
by Bill Jewell on 12-14-2011 at 11:54 pm

SICAS (Semiconductor Industry Capacity Statistics) has released its 3Q 2011 data, available through the SIA at: SICAS data . Beginning with 2Q 2011 the SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or United Microelectronics Corporation… Read More


MEMS layout and automation

MEMS layout and automation
by Daniel Payne on 12-14-2011 at 11:12 am

At a webinar today I listened and learned about how a tool called L-Edit can be used to layout MEMS designs plus automate the task to be more productive. I can see how the history of IC layout editing is now being repeated with MEMS because in the earliest IC layout tools we could only do manual entry of polygons, then gradually we got cells… Read More


iLVS: Improving LVS Usability at Advanced Nodes

iLVS: Improving LVS Usability at Advanced Nodes
by glforte on 12-13-2011 at 4:54 pm

LVS Challenges at Advanced Nodes

Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. As the number of layers and layer derivations increases the complexity of devices, especially Layout Dependent… Read More


IP-SoC 2011 Trip Report: IP again, new ASSP model, security, cache coherence and more

IP-SoC 2011 Trip Report: IP again, new ASSP model, security, cache coherence and more
by Eric Esteve on 12-13-2011 at 9:05 am

For the 20[SUP]th[/SUP] anniversary of IP-SoC, we had about ten presentations, most being really interesting; the conference has provided globally a very good level of information, speakers coming from various places like China, Belarus, The University of Aizu (Japan), University of Sao Paulo (Brazil), Silesian and Warsaw… Read More