Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Secure-IC at the 2025 Design Automation Conference #62DACSecure-IC at DAC 2025: Building Trust into Tomorrow’s…Read More
The Sondrel transformation to Aion SIlicon!Ollie is a commercially astute senior leader with…Read More
Keysight at the 2025 Design Automation Conference #62DACKeysight Showcases AI-Ready EDA and Multi-Physics Innovation at…Read More
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A catchy phrase used by bloggers and journalists these days is “Internet of Things“, or IoT if you prefer acronyms. All of this is made possible by EDA tools in the hands of SoC designers to create useful products like my Jawbone ICON bluetooth headset. Tonight I discovered that I could customize my bluetooth headset… Read More
Matt Elmore has a two-part blog about the growing complexity of signal integrity analysis, both on the chip itself and the increasingly complex analysis required to make sure that signals (and power) get in and out of the chip from the board cleanly, especially to memory, which requires simultaneous analysis of chip-package-system… Read More
Electronic Design and Solutions Fair (EDSF) was held in Yokohama Japan from Wednesday to Friday last week. It was held at the Pacifico Hotel, somewhere I have stayed several times, not far from the Yokohama branch of Hard Rock Cafe and, what used to be at least, the biggest ferris-wheel in the world.
Atrenta was one of the many companies… Read More
Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other… Read More
The announcement that Paul Otellini will step down in May 2013 is extraordinary in the history of the way Intel makes CEO transitions. They are thoughtful, deliberate and years in the making, unlike today’s announcement. Twenty years ago Otellini and Andy Bryant were in the top echelon of Andy Grove’s executive team and … Read More
Ever since the failed Intel PR stunt where Mark Bohr suggested that the fabless semiconductor ecosystem was collapsing I have been researching and writing about it. The results will be a book co-authored by Paul McLellan. You may have noticed the “Brief History of” blogs on SemiWiki which basically outline the book. If not, start… Read More
Yesterday, I clicked “like” on a LinkedIn post with the title “TI Cuts 1,700 Jobs”. Today, I read the analysis and pulled out Social Distortion’s “Still Alive” for inspiration. I’ve been through this more than once. For them it’s not like-worthy, and I feel their sting.
The part of the post I liked was the comment: “This is good for … Read More
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, a new IEEE P1687 standard is being defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three major EDA vendors. This new standard, also called… Read More
Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.
You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping… Read More
Finding and debugging failures on integrated circuits has become increasingly difficult. Two sessions at ISTFA (International Symposium for Testing and Failure Analysis) on Thursday address the current best practices and research directions of diagnosis.
The first was a tutorial this morning by Mentor Graphics luminary… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot