2026 Ceva Edge Symposium: Building Intelligence Beyond the CloudThe 2026 Ceva Edge Symposium will bring together…Read More
HBM’s Second Act: When Memory Starts ThinkingSamsung’s Hot Chips 2026 presentation, “HBM Base Die:…Read More
NVIDIA Vera: Rebuilding the CPU for Agentic AISource: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera…Read More
High-NA EUV Moves From Experiment to ManufacturingIntel Foundry and ASML say high-numerical-aperture extreme-ultraviolet lithography…Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical SignificanceASML and TSMC’s proposed shift from 6-inch to…Read More
– AMAT has OK Q but horrible guide as China & Leading edge drop
– China finally chokes on indigestion & export issues -$500M hit
– TSMC trims on fab timing causing leading edge to slow -$500M hit
– Cycle which had slowed to single digits has rolled over to negative
Russell (Russ) Garcia is a veteran technology executive with over 30 years of leadership experience in semiconductors, telecommunications, and advanced electronics. As CEO of Menlo Microsystems, he has led the commercialization of disruptive MEMS switch technology across RF, digital, and power systems.
Previously, Russ… Read More
In this episode of the Semiconductor Insiders video series, Dan is joined by John Elliott, security applications engineer from Cycuity. With 35 years of EDA experience, John’s current focus is on security assurance of hardware designs.
John explains the importance of security coverage in the new global marketplace. He describes… Read More
Dan is joined by Mamta Gupta, She leads the Security Product Marketing, Datacenter and the Communications Segment Marketing Teams at Lattice. She brings with her over 20 years of FPGA experience in product development with special focus on security, aerospace and defense segments.
Dan explores the growing area of cybersecurity… Read More
The global semiconductor market in 2Q 2025 was $180 billion, up 7.8% from 1Q 2025 and up 19.6% from 2Q 2024, according to WSTS. 2Q 2025 marked the sixth consecutive quarter with year-to-year growth of over 18%.
The table below shows the top twenty semiconductor companies by revenue. The list includes companies which sell devices… Read More
Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. … Read More
As multi-die and chiplet-based system designs become more prevalent in advanced electronics, much of the focus has been on physical design challenges. However, verification—particularly functional correctness and interoperability of inter-die connections—is just as critical. Interfaces such as UCIe or custom interconnects… Read More
Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying… Read More
Problem & significance.
Single-source shortest paths (SSSP) on directed graphs with non-negative real weights is a pillar of graph algorithms. For decades, the textbook gold standard has been Dijkstra’s algorithm with good heaps, running in the comparison-addition model (only comparisons and additions on weights).… Read More
According to a recent Samtec whitepaper, in high-data-rate (HDR) architectures, where signals traverse tens to hundreds of gigabits per second, “cable management” isn’t a housekeeping chore, it’s a first-order design variable. The mechanical path a cable takes directly influences channel loss, crosstalk, reliability,
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ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance