800x100 Webinar (1)

Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
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  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
  • Read More

    TSMC Financial Update Q4 2012!

    TSMC Financial Update Q4 2012!
    by Daniel Nenni on 11-11-2012 at 4:00 pm

    The weather in Taiwan last week was very nice, not too hot but certainly not cold. The same could be said for the TSM stock which broke $16 after the October financial report where TSMC reported a sales increase of 15% over September. Revenues for this year thus far increased 19% over last year so why isn’t TSM stock at $20 like I predicted… Read More


    Smartphone Market Share

    Smartphone Market Share
    by Paul McLellan on 11-09-2012 at 12:47 pm

    The numbers for smartphone sales in Q3 are starting to roll in. These are in units and not yet revenue (let alone profit) numbers although everyone down to Sony is for sure profitable. Samsung is running away with the volume, selling more than Apple, Huawei and Sony put together. One name that is missing is Motorola (Google) which … Read More


    Carbon has Six Weeks of ARM, not to Mention Imagination and MIPS

    Carbon has Six Weeks of ARM, not to Mention Imagination and MIPS
    by Paul McLellan on 11-09-2012 at 12:18 pm

    As George E.P. Box said, “essentially all models are wrong but some are useful.” That is certainly the case with Carbon’s models. For processors they have two models, one that is fast (but not timing-accurate) and one that is accurate (but not fast). But both are useful.

    Carbon attended the ARM TechCon in Santa… Read More


    ICCAD at 30: Alberto Looks Back and Forward

    ICCAD at 30: Alberto Looks Back and Forward
    by Paul McLellan on 11-08-2012 at 8:10 pm

    At ICCAD earlier this week, CEDA sponsored a talk by Alberto Sangiovanni-Vincentelli looking back over the last 30 years (it is the 30th anniversary of ICCAD) and looking to the future. As is always the case in these sorts of presentations, the retrospective contained a lot more detail than the going forward part. Clayton Christensen… Read More


    IJTAG, Testing Large SoCs

    IJTAG, Testing Large SoCs
    by Paul McLellan on 11-08-2012 at 5:57 pm

    Test is the Rodney Dangerfield of EDA, it doesn’t get any respect. All designs need to be tested but somehow synthesis, routing, analog layout and the rest are the sexy areas. In my spoof all purpose EDA keynote address I even dissed it:You are short on time so slip in a quick mention of manufacturing test. Who knows anything … Read More


    ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program

    ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program
    by Eric Esteve on 11-07-2012 at 12:17 pm

    More than one year old now, TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. This soft IP quality program has been the first to be initiated by a Silicon foundry on other than “Hard IP”,Read More


    Solido and TSMC for 6-Sigma Memory Design

    Solido and TSMC for 6-Sigma Memory Design
    by Daniel Nenni on 11-06-2012 at 8:30 pm

    Solido Design Automation and TSMC recently published an article in EE Times describing how Solido’s High-Sigma Monte Carlo tool is used with TSMC PDK’s to achieve high-yield, high-performance memory design. This project has been a big part of my life for the past three years and it is time for a victory lap!

    In TSMC 28nm, 20nm and … Read More


    Embedding 100K probes in FPGA-based prototypes

    Embedding 100K probes in FPGA-based prototypes
    by Don Dingee on 11-06-2012 at 8:15 pm

    As RTL designs in FPGA-based ASIC prototypes get bigger and bigger, the visibility into what is happening inside the IP is dropping at a frightening rate. Where designers once had several hundred observation probes per million gates, those same several hundred probes – or fewer if deeper signal captures are needed – are now spread… Read More


    A Most Significant Man

    A Most Significant Man
    by Beth Martin on 11-06-2012 at 8:10 pm

    Most of us live perfectly good lives without distinction, fame, or note. Others rack up the honors, filling their walls and resumes with recognition of their brilliance. Like Dr. Janusz Rajski.

    Rajski is the director of engineering for the test products at Mentor Graphics, an IEEE Fellow, and the inventor of embedded deterministic… Read More