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Current Timing Closure Techniques Can’t Scale – Requires New Solution

Current Timing Closure Techniques Can’t Scale – Requires New Solution
by Daniel Nenni on 10-16-2012 at 8:30 pm


There’s a nice article on timing closure by Dr. Jason Xing, Vice President of Engineering at ICScape Inc. on the Chip Design website. Not familiar with ICScape? Paul McLellan called ICScape the The Biggest EDA Company You’ve Never Heard Ofand Daniel Payne did Schematic, IC Layout, Clock and Timing Closure from ICScape atRead More


Altera’s Real Impact with ARM based SOC FPGAs

Altera’s Real Impact with ARM based SOC FPGAs
by Ed McKernan on 10-16-2012 at 8:15 pm

At the annual Linley Processor Conference this past week a number of chip vendors proposed a raft of new networking solutions directed at solving today’s bandwidth issues. Perhaps the overall highlight of the conference was the recognition by Keynote Speaker Linley Gwennap of the shift that is taking place towards ARM based solutions.… Read More


Laker3 in TSMC 20nm Reference Flow

Laker3 in TSMC 20nm Reference Flow
by Paul McLellan on 10-16-2012 at 8:10 pm

SpringSoft, soon to be part of Synopsys but officially still a separate company for now, just announced that Laker[SUP]3[/SUP], the third generation of their layout product family, is featured in TSMC’s 20nm Custom Reference Flow.

Laker 20nm advancements include new double patterning-aware design and voltage-dependent… Read More


Kaufman Award Dinner at 50th DAC in Austin

Kaufman Award Dinner at 50th DAC in Austin
by Paul McLellan on 10-16-2012 at 8:05 pm

In past years the Kaufman award, the most prestigious in EDA, has been announced around September and presented during a dinner in October or November in Silicon Valley. EDAC and CEDA, the sponsors of the award, have just announced that this time the award dinner will take place in Austin at the 50th DAC following the early Sunday … Read More


Oct. 18 Non-Volatile Memory Webinar, IBM validates OTP for Foundry program, & New Low-Risk Evaluation License

Oct. 18 Non-Volatile Memory Webinar, IBM validates OTP for Foundry program, & New Low-Risk Evaluation License
by Daniel Nenni on 10-16-2012 at 9:37 am

As the temperature drops and the bright red maple leaves have begun to pile up, so has the stack of projects at Novocell. If you are expecting to utilize their high reliability, easy-to-integrate OTP in a project taping out in late Q4 or early Q1, NOW is the time to contact them.

OTP Overview Webinar Thurs, Oct 18

Novocell and global … Read More


After 10 years promoting crossbar switch for interconnects, Sonics finally admit that NoC is better

After 10 years promoting crossbar switch for interconnects, Sonics finally admit that NoC is better
by Eric Esteve on 10-15-2012 at 11:27 am

Network on Chip (NoC) technology is probably one of the most fascinating new concepts that has been developed and is implemented in real chips. NoC can be integrated into various System on Chip (SOC), targeting several market segment: Video Processing, Consumer Electronics, Automotive, Networking, Multimedia (digital TV),… Read More


Apple and The Road Ahead to Building an x86 Processor

Apple and The Road Ahead to Building an x86 Processor
by Ed McKernan on 10-15-2012 at 9:00 am


A small blurb last week announced that Apple had hired Jim Mergard away from Samsung after just 15 months on the job. Previously to that he was a 16-year AMD veteran who headed up their low power x86 Brazos processor team. In near synchronicity, AMD hired Famed Apple Designer Jim Keller to be its chief microprocessor architect. When… Read More


A brief History of Mobile: Generations 1 and 2

A brief History of Mobile: Generations 1 and 2
by Paul McLellan on 10-14-2012 at 9:00 pm

Mobile is one of the biggest markets for semiconductor, especially if you count not just mobile handsets but also the base-station infrastructure. No technology has ever been adopted so fast and so completely. There are approximately the same number of mobile phone accounts as there are people in the world. A few people have more… Read More


Power Integrity Challenges for High Speed and High Frequency Designs

Power Integrity Challenges for High Speed and High Frequency Designs
by Daniel Nenni on 10-14-2012 at 8:30 pm

There is an interesting discussion on the LinkedIn SoC Power Integrity Group in regards to the power integrity challenges for high speed and high frequency designs. More specifically, the additional attention an on-chip power delivery network (PDN) requires as the operating frequency of ICs and SoCs increases.

The PDN has to… Read More