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Semiconductor Industry Standards Update 2012

Semiconductor Industry Standards Update 2012
by Daniel Nenni on 05-27-2012 at 12:11 am

Standards have been proven to reduce cost of operations, drive greater process efficiencies and offer greater opportunities for start-up companies to infuse fresh technology in the design and manufacturing of IC’s. Si2 standards have been targeted to resolve “pinch-points” in the overall semiconductor supply chain… Read More


Apache Ansys Update 2012

Apache Ansys Update 2012
by Daniel Nenni on 05-26-2012 at 9:26 pm

Apache is one of the brightest stars in the EDA universe. Paul McLellan has done a nice job covering them before and after the Ansys acquisition. Check out the Apache SemiWiki landing page HERE. The Apache wikis are also very well done and it has been a pleasure working with the Apache marketing team. Expect more innovative things … Read More


The Apple iPhone5 Olympic Launch Scenario

The Apple iPhone5 Olympic Launch Scenario
by Ed McKernan on 05-25-2012 at 9:23 am

Just days after I posted a blog on an early September iPhone 5 launch, the spies from Asia started flooding the rumor mills with Apple supply chain maneuvers that are not easily hidden suggesting that D-Day logistics are farther along than we imagined. This flood of information, coupled with the heightened Samsung-Apple Battle… Read More


3D Transistors and IC Extraction Tools

3D Transistors and IC Extraction Tools
by Daniel Payne on 05-24-2012 at 4:05 pm

Have you ever heard of a Super Pillar Transistor? It’s one of many emerging 3D transistor types, like Intel’s popular FinFET device.

In the race to continuously improve MOS transistors, these new 3D transistor structures pose challenges to the established IC extraction tool flows.

Foundries have to provide an Effective… Read More


Solido Design Automation Update 2012

Solido Design Automation Update 2012
by Daniel Nenni on 05-24-2012 at 10:27 am

Having spent a considerable amount of time with Solido, they were one of the founding members of SemiWiki, I can tell you that at 20nm the Variation Designer Platform is a critical part of the emerging 20nm design methodology. You can read more on Solido’s SemiWiki landing page HERE. It is well worth the click.

With technology… Read More


Analog FastSPICE added to Tanner EDA

Analog FastSPICE added to Tanner EDA
by Daniel Payne on 05-24-2012 at 10:18 am

Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.

This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.

This year they’ve… Read More


Network on Chip in Automotive: Arteris

Network on Chip in Automotive: Arteris
by Eric Esteve on 05-24-2012 at 9:20 am

The recent announcement from Arteris that iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems is very interesting, as it shows that SoC designed for the Automotive market segment also require advanced … Read More


After Planning Comes Implementation for Pulsic

After Planning Comes Implementation for Pulsic
by Paul McLellan on 05-24-2012 at 7:00 am

Automation for digital design has been mainstream for a couple of decades but place and route for analog is still in its infancy. Many attempts have been made over the years to automate analog design in one way and another, the bodies are piled up on the hillside. Much analog design is still largely done with custom layout and circuit… Read More


Software-based Wi-Fi: DSP IP core

Software-based Wi-Fi: DSP IP core
by Eric Esteve on 05-23-2012 at 10:05 am

The recent announcement from CEVA that it has joined the Wi-Fi Alliance® to further advocate for a software-based Wi-Fi® strategy shows that the new CEVA-XC4000 DSP can be used in various communication protocols, not limited to the traditional baseband processing for the wireless handset phone, where DSP IP core usage is massive.… Read More


Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap
by Daniel Nenni on 05-22-2012 at 9:00 pm

The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the… Read More