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Semiconductor Expert Forum

Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han

Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han
by Daniel Nenni on 08-09-2024 at 10:00 am
Categories: EDA, Synopsys

Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More

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CEO Interview: Yogish Kode of Glide Systems

CEO Interview: Yogish Kode of Glide Systems
by Daniel Nenni on 08-09-2024 at 6:00 am
Categories: AI, CEO Interviews

Yogish Kode

Yogish Kode is a senior solutions architect with substantial experience in product lifecycle management for over 20 years. His focus has been on semiconductor PLM and IP management. Prior to founding Glide Systems, he was a global solutions architect at Dassault Systèmes, an IT lead at Xilinx, and a senior programmer/analyst… Read More

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Design Automation Conference #61 Results

Design Automation Conference #61 Results
by Daniel Nenni on 08-08-2024 at 10:00 am
Categories: Events

IMG 3273

This was my 40th Design Automation Conference and based on my follow-up conversations inside the semiconductor ecosystem it did not disappoint. The gauge I use for exhibitors is “qualified customer engagements” that may result in the sale of their products. This DAC was the best for that metric since the pandemic, absolutely.… Read More

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Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
by Fred Chen on 08-08-2024 at 6:00 am
Categories: Lithography, TSMC
1 Comment

Application Specific Lithography I

At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track … Read More

Podcast EP239: The Future of Verification for Advanced Systems with Dave Kelf

Podcast EP239: The Future of Verification for Advanced Systems with Dave Kelf
by Daniel Nenni on 08-07-2024 at 8:00 am
Categories: Breker Verification Systems, EDA

Dan is joined by Dave Kelf, CEO of Breker Verification Systems, whose product portfolio solves challenges across the functional verification process for large, complex semiconductors. Dave has deep experience with semiconductor design and verification with management and executive level positions at Cadence, Synopsys,… Read More

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The Future of Logic Equivalence Checking

The Future of Logic Equivalence Checking
by Bernard Murphy on 08-07-2024 at 6:00 am
Categories: AI, Cadence, EDA

LEC concept

Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More

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Aniah and Electrical Rule Checking (ERC) #61DAC

Aniah and Electrical Rule Checking (ERC) #61DAC
by Daniel Payne on 08-06-2024 at 10:00 am
Categories: Aniah, EDA

Aniah #61DAC min

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More

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Writing Better Code More Quickly with an IDE and Linting

Writing Better Code More Quickly with an IDE and Linting
by Tom Anderson on 08-06-2024 at 6:00 am
Categories: AMIQ EDA, EDA

Lightmatter

As a technical marketing consultant, I always enjoy the chance to talk to hands-on users of my clients’ electronic design automation (EDA) tools to “see how the sausage is made” on actual projects. Cristian Amitroaie, CEO of AMIQ EDA, recently connected me with Verification and Infrastructure Manager Dan Cohen and Verification… Read More

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3D IC Design Ecosystem Panel at #61DAC

3D IC Design Ecosystem Panel at #61DAC
by Daniel Payne on 08-05-2024 at 10:00 am
Categories: Foundries, Intel Foundry
1 Comment

bits per joule min

At #61DAC our very own Daniel Nenni from SemiWiki moderated an informative panel discussion on the topic of 3D IC Design Ecosystem. Panelists included: Deepak Kulkarni – AMD, Lalitha Immaneni – Intel Foundry, Trupti Deshpande – Qualcomm, Rob Aitken – CHIPS, Puneet Gupta – UCLA, Dragomir Milojevic – imec. Each panelist had a brief… Read More

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Mitigating AI Data Bottlenecks with PCIe 7.0

Mitigating AI Data Bottlenecks with PCIe 7.0
by Kalar Rajendiran on 08-05-2024 at 6:00 am
Categories: AI, EDA, IP, Synopsys

Mitigating AI Data Bottlenecks with PCIe 7.0 LinkedIn Event

During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More