Unless you have been living under a rock for the last decade, you can’t help but notice the increased importance of RF: bluetooth, WiFi, 3G, LTE, NFC, RFID and more. There is a lot of digital design associated with these standards, especially the highest bandwidth ones, but they also all contain a radio, often called a modem.… Read More
Reachability in Analog and AMS. Innovation in VerificationCan a combination of learning-based surrogate models plus…Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural PivotIn 2003, legendary computer architect Michael J. Flynn…Read More
Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping SystemQualifying an AI-class RISC-V SoC demands proving that…Read More
DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
CDC Verification: A Must for IP and SoCs
In the modern SoC era, verification is no longer a post-design activity. The verification strategy must be planned much earlier in the design cycle; otherwise the verification closure can become a never ending problem. Moreover, verification which appears to be complete may actually be incomplete because of undetected issues… Read More
Getting a Grip on the Internet of Things
QuickLogic’s CTO Tim Saxe gave a keynote Getting a Grip on the Internet of Things at the IoT Summit last week.
He started by relating how things have changed over the last 3 years when he talks to customers.
- Three years ago it was sensor hubs in smartphones and the power budget was 3mW (so one day between re-charging, something
Cadence’s New Implementation System Promises Better TAT and PPA
On Tuesday Cadence made a big announcement about their new physical implementation offering, Innovus, during the keynote address at the CDNLive event in Silicon Valley. Cadence CEO Lip-Bu Tan alluded to it during his kick off talk, and next up Anirudh Devgan, Senior Vice President, Digital & Signoff Group, filled in more … Read More
How many coats cover this SoC?
“Most interior paint covers with one coat.” Back when there was something called a newspaper, this was an actual blurb in the home improvement pages, section 3, part 8, page 5 of the Chicago Tribune on Sunday, August 13, 1961. Even then, marketers were catering to consumers looking to cut corners and save time, and one-coat coverage… Read More
SoCs More Vulnerable to ESD at Lower Nodes
Electro Static Discharge (ESD) has been a major cause of failures in electronic devices. As the electronic devices have moved towards high density SoCs accommodating ever increasing number of gates at lower process nodes, their vulnerability to ESD effects has only increased. Among the reasons for ESD failures in SoCs, device… Read More
Innovus: Cadence’s Next Generation Implementation System
Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then… Read More
On-Chip Power Integrity Analysis Moves to the Package
Power regimes for contemporary SOC’s now include a large number of voltage domains. Rail voltages are matched closely to the performance and power requirements of various portions of the design. Indeed, some of the supply voltages are so low that the noise margins in these domains is exceedingly low. Higher voltage domains are… Read More
Altera 14nm and 10nm Update!
In preparation for this blog I Googled around to get the latest information made available by Altera to see if it matches up with what I know from discussions amongst the fabless semiconductor ecosystem companies. Unfortunately when I Googled Altera+20nm+14nm the first three entries from the Altera website were Error 404 Page… Read More
FinFET Design Enablement
We read about FinFET technology in the semiconductor press daily now, thanks to Intel introducing their TriGate transistors starting in 2011 and creating a race with foundries and IDMs to switch from planar CMOS nodes. To get some perspective about the progress of FinFET IP and EDA tools I spoke with two experts from Synopsys, Swami… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot