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ARM & Cadence IP Partnership for Faster SoC Design

ARM & Cadence IP Partnership for Faster SoC Design
by Eric Esteve on 03-18-2015 at 9:50 am

IP vendors always try to create differentiation, especially when designing protocol based IP. You can differentiate by building the most performing controller but you will probably miss the expectation of these customers who don’t search for performance but just compliance to a specific standard. Or the vendor may want to design… Read More


SEMI: All This and Breakfast Too

SEMI: All This and Breakfast Too
by Paul McLellan on 03-18-2015 at 7:00 am

Are you interested in any of these?

  • Internet of Things
  • Trends and Forecast for Fabs
  • Inflections Points
  • Semiconductor CAPEX
  • Cost Effective Scaling
  • Prospects for 450mm
  • Future of EUV
  • Mobile Machine Learning
  • Robotics/Drones
  • Cybersecurity
  • Used Equipment Markets
  • World Fab Databases
  • Free breakfast

No? Then I think you got the wrong… Read More


Webinar: Choosing IP for your next IoT Design

Webinar: Choosing IP for your next IoT Design
by Daniel Payne on 03-17-2015 at 8:00 pm

My favorite IoT device is a cycle-computer from CatEyeand it has GPS for tracking my bike routes, and an LCD display that shows me speed, cadence, heart rate and time. After each ride I connect my CatEye device to a USB connector, upload my data to Strava.com, and then see how I’m doing versus other cyclists and my own personal… Read More


Exploring IP You Didn’t Design Yourself

Exploring IP You Didn’t Design Yourself
by Paul McLellan on 03-17-2015 at 7:00 am

Starvision Pro from Concept Engineering is a bit like one of those Leatherman multi-tools, it has a huge number of different functions, some of them fairly specialized but nonetheless incredibly useful. Many of these functions are unique to Starvision Pro, with nothing else like it on the market. Some new videos, produced by EDA… Read More


Mapping Focus and Dose onto BEOL Fabrication Effects

Mapping Focus and Dose onto BEOL Fabrication Effects
by Tom Simon on 03-16-2015 at 7:00 pm

With today’s ArF based lithography using 193nm wavelength light, we are hard up against the limitations imposed by the Raleigh equation. Numerous clever things have been devised to maximize yield and reduce feature size. These include 2 beam lithography, multiple patterning, immersion litho processes to improve NA, thinner… Read More


FD-SOI Foundry

FD-SOI Foundry
by Paul McLellan on 03-16-2015 at 7:00 am

At the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the Pied Piper valued… Read More


Apple Leaks Chip Sources?

Apple Leaks Chip Sources?
by Daniel Nenni on 03-15-2015 at 10:00 pm

Take a look at the figure below and tell me this information did not come from inside Apple. The question is: Was it voluntary or involuntary? Inquiring minds want to know! There are some minor surprises which I will get to in a minute but the actual source information is spot on to what I have heard the past few quarters. This spicy little… Read More


Will the IC Market Growth Rate Stagnate in 2015?

Will the IC Market Growth Rate Stagnate in 2015?
by Pawan Fangaria on 03-15-2015 at 7:00 pm

In my last blog here, I talked about last 30+ years of semiconductor IC market. While we have seen this market growing at CAGR of ~9% over last 30+ years, the CAGR of current decade is expected to be at just ~4%. Although the base size of the overall semiconductor IC market is quite healthy, expected to be at ~$378B by 2019, we cannot hope… Read More


Lake Tahoe: The Center of ESD Innovation

Lake Tahoe: The Center of ESD Innovation
by glforte on 03-15-2015 at 1:00 pm

Almost anyone that is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness… Read More


Shifting Chip Design Left!

Shifting Chip Design Left!
by Daniel Nenni on 03-15-2015 at 7:00 am

In the traditional sense “Shift Left” is the process of making things simpler in an effort to make things faster. Shift Left was the theme of theDVCon keynote last week delivered by Synopsys co-founder and co-CEO Aart de Geus which is right on topic when it comes to modern semiconductor design and manufacturing, absolutely.

KEYNOTE:Read More