After spending my first year learning a great deal about Diffusion and completing my orientation at Fairchild, I was moved to the 3″ Photolithography area as a sustaining engineer. As with the Diffusion area, being a sustaining engineer in Photo meant dispositioning lots on hold and making process improvements as needed.
The Photo area was arranged as a series of seven tunnels, each being approximately 15 feet wide and approximately 70 feet long. Each tunnel contained various photo and etch equipment that supported the following process steps:
1. Photoresist prime/coat/softbake – III tracks
2. UV exposure – Perkin Elmer projection aligners
3. Photoresist develop and rinse – III tracks
4. Hardbake – Blue M ovens
5. Optical inspection – Microscope
6. Wet Etch – Buffered Oxide Etch for oxide layers, Metal Etch mixture for Metal layers
7. Photoresist Strip – Sulfuric Peroxide heated wet bath (100C)
8. Final Optical Inspection – Microscope
As you can imagine, each photo tunnel was crowded with equipment, production operators, workleaders, equipment and process technicians and engineers. At any one time, I would estimate 15 people to be present in each tunnel. Although I never considered the area to be unsafe, I do remember the strong smell of negative and positive photoresists, xylene, n-butyl acetate, acetone, etc. The equipment and controls were not nearly as developed and refined as is commonplace today. The process equipment was semi-automated. For example, a resist coat operator would place a cassette of 25 wafers on the load elevator of the III and the tool would load and center the wafer onto the coater vacuum chuck. The vacuum chuck would then lower into the spinner cup and would spin at a programmed spin speed to apply the HMDS primer and coat the wafer with photoresist to a thickness of approximately 8000A (Hunt negative resist).
Once complete, the wafers would be baked in an infrared belt oven and loaded onto an exit cassette. The operators would then unload the completed lot and move to the next operation (align and UV exposure). The primary equipment we used to align and expose wafers were Perkin Elmer 140 aligners. These tools were workhorses in the industry throughout the 1980s. Light was generated using a mercury lamp which had a UV spectrum throughout the 365nm to 436nm range. UV exposure was accomplished by scanning the wafers using a projected mask image. Once complete, wafers were then developed and hard baked using III track developer systems. All wafers were then inspected under a microscope to ensure the exposed image was properly aligned and fully developed.
The photo process in those days left much to be desired. The largest single problem I remember was negative resist scumming which caused a thin top layer of resist to peel off and deposit itself in a random fashion across developed window openings, potentially causing etch problems. As a result, the photo process had a very high rework rate, running anywhere from 5% to 50%! After months of process debug effort, we determined the problem was caused by high levels of nitrous oxide (NOx) which was coming from the exhaust of taxying jet planes at the jetport adjacent to the factory. Eventually the problem was corrected by a combination of process modification and modification of the fab air intake.
The etch processes employed during this time were predominantly wet chemical etch mixtures for etching silicon oxides and aluminum. Barrel etchers from a company named LFE were used to etch patterned CVD nitride. Once the etch process was complete, the photoresist was stripped off using either a sulfuric peroxide piranha solution (for oxide mask levels) or an LFE barrel asher (for layers post metal processing). The sulfuric peroxide solution was vastly preferred in my opinion because it effectively removed the photoresist without leaving high levels of ionic, inorganic contamination, such as potassium and sodium.
The barrel asher process, on the other hand, effectively removed the resist but also induced high ionic contamination which diffused into the wafer during the high temperature (> 200C) asher overstrip step. Ionic contamination was a serious concern that could cause reliability degradation of the device. We measured ionic contaminant levels using a CV plotter and this method remains in use today. Wafers stripped using the barrel ashers could have ionic contamination levels in excess of 2e12 ions/sq. cm while wafers stripped using sulfuric peroxide typically exhibited levels below 3e10 ions/sq. cm.
Yield improvement was always a key focus area for operational improvement. During the early 1980’s we developed and implemented pellicles onto our photomasks. Pellicles are thin transparent nitrocellulose membranes, supported by a circular frame, that are attached over the chrome plated photomasks to protect the masks from particles. Instead of airborne particles landing on the photomask surface, they would land on the pellicle surface and would not print onto the wafer since the pellicle membrane was out of the focus location. The very first application of pellicles at the South Portland fab resulted in a 5% die yield improvement on the LS157 (low power schottky) product, a significant achievement. This strong yield improvement indicated the fabrication area had a very high defect density and could benefit from other defect reduction process improvements.
One such improvement involved wafer scrubbing. During the 1980’s, much effort was placed on cleanroom contamination control since defect density levels were a significant yield inhibitor. Wafer scrubbing was used as a local containment measure until the general airborne and process contamination levels could be reduced to entitlement levels. The image below shows the first page of an internal memorandum from 1982 whereby we were working to implement a high pressure water scrub process to clean contaminated wafers prior to the photo process. Wafer scrub processes became somewhat commonplace until the fab environments and processes were sufficiently clean and the scrubbers no longer provided benefit (and actually did more harm than good).
At this time, Fairchild was owned by Schlumberger, a well-known French firm specializing in the oil industry. Financially, Fairchild was struggling although the South Portland fab site had two high capacity fabs (3″ and 4″ wafers) that were nearly filled to capacity. Competition within the industry was fierce and our primary competitor, Texas Instruments, had well developed advanced schottky (AS) and Advanced Low Power Schottky (ALS) logic product lines to compete with our FAST (Fairchild Advanced Schottky Technology) bipolar product line. FAST was a winning technology for Fairchild and was our first logic family to be based on the Isoplanar oxide isolation process, patented by one of our key technologists, Doug Peltzer.
Oxide isolation reduced device junction capacitance levels associated with previous technologies and supported high speed device performance. The technique was first used by Fairchild on their RAM memories back in the early 70’s but this was the first use on logic devices. The FAST product line started production back in the 70’s and proved to be a big money-maker for Fairchild, with production shipments continuing throughout much of the 1990’s.
The longevity of the logic product offerings from 30 years ago stands in stark contrast to the analog product offerings of today which require fast and efficient development cycles and have a life cycle of 5 years or less.
I remember the early 1980’s as a very exciting time in the industry. The fabrication processes and associated equipment were relatively unrefined with countless opportunities for improvement. But the challenges for improvement offered tremendous opportunity. Unlike the relatively few large equipment companies of today (Varian, Applied, Novellus, TEL, ASM, etc), there were many equipment vendors in existence and their equipment designs varied widely. Equipment uptimes were low by today’s standards, and it was not uncommon to have average uptimes in the 60% – 70% range. It wasn’t until the late 80’s when Sematech came online that significant consolidation of the equipment suppliers took place.
The work environment in the early 80’s was challenging yet a great deal of fun. Working in Fab Operations, particularly as a sustaining engineer, required that we worked long hours and responded to process problem calls at all hours of the night. There were weekly yield improvement meetings where fab, survival and die yield trends were reviewed and actions assigned. Projects were spawned to drive process and yield improvement. Engineers who were responsible for these projects were expected to present status updates at these weekly meetings. Progress was expected and the pressures were great. You were expected to be on time for the start of the meeting and be well prepared. Management was supportive but demanding and they were not shy about letting you know when your efforts didn’t measure up. I was lucky enough to be enrolled in a Dale Carnegie training class in 1981 and this helped me to overcome my fear of public speaking. It also helped me to organize my thoughts and be more efficient with words.
Despite all the pressures of the job including presenting project status to management, it was all well worth it. Many of the engineers, technicians and operators at the South Portland plant were young and in our 20’s and spent fun times together outside of work. We all worked hard and played hard. We used to have manufacturing vs. engineering softball games on Friday afternoons after work with bragging rights to the winners and the losers having to buy the beers. We forged lasting relationships and developed a strong sense of teamwork that benefited both our company and ourselves. We were all proud to work for Fairchild. The semiconductor industry was still relatively young and constantly changing. There was little chance of becoming bored.
….more to follow.
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