Today, an SoC is seen in the context of an optimized assembly of IPs; it’s no more a single monolithic chip design. It’s very common to see an ARM processor IP along with an interconnect IP, a memory IP, and couple of buses and interfaces IP in an SoC. Although the SoC seems to be an integrated collection of IPs, it can be very complex and… Read More
Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping SystemQualifying an AI-class RISC-V SoC demands proving that…Read More
DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
High Level Synthesis. Are We There Yet?
High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More
Further Delays for Intel 10nm?
Intel’s 10nm may be reliving the 14nm elongated delay issue-
Schedules & tool delivery may be pushed even deeper into 2016-
Meanwhile Samsung & TSMC press on-
Could Intel be embarrassed?
… Read More
I Don’t Know Much About Aart…
Actually, like anyone who has been in EDA for more than a decade or two (or three) I know quite a bit about Aart. But I still learned quite a bit about his views at the Fireside Chat at DAC where Ed Sperling talked to Aart for three-quarters of an hour.
Aart has a great talent at taking various small trends in the industry and aggregating … Read More
Eyes Meet Innovations at DAC
It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D… Read More
Design Data Management: An Analog IP Porting Case Study
IQ-Analog Corp. offers “off-the-shelf” data converter intellectual property (IP) for multiple foundries. The San Diego, California–based semiconductor design firm also provides analog front-end (AFE) technology that it tailors according to customer needs. And that’s where the dilemma begins.
IQ-Analog’s… Read More
Extending EUV Lithography
I have previously written about SPIE day 1 and 2 so I want to wrap up my coverage with some impressions from days 3 and 4. My single biggest take away from the conference is that EUV has made tremendous progress in the last 12 months. Last year the mood of the conference was in my opinion pessimistic with respect to EUV, this year the mood… Read More
eSilicon@Samsung: ASIC Design, IP Enablement, and Cloud Platform
Earlier this week at DAC, Javier DeLaCruz of eSilicon presented at the Samsung booth. They presented an introduction to what eSilicon does. However, since what they do has changed over the years it is useful to recap. If you know about eSilicon then you probably think of them as a fabless ASIC company. The old ASIC model back in the … Read More
ARM and frog Team up with UNICEF to Foster Creation of Wearables for the Developing World
When the term wearables is mentioned most people’s first thoughts go to devices like the Apple Watch, Fitbit Flex, or Nike Fuel Band. Wearables such as these solve first-world problems like how much exercise am I getting, or what is my heart rate. The developed world drives the development of new technology in most cases, and wearables… Read More
Application Specific Integrated Comedy
Tuesday night I got to meet an old colleague. OK, this is DAC, that is hardly a story. I was at the Synopsys media dinner and John Koeter handed out free wristbands to the Stars of IP party taking place later that evening. Remember, Synopsys is #3 in IP overall and #1 in interface IP. Talking of which, earlier in the day I was at the Synopsys… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot