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Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More


Tcl scripts and managing messages in ASIC & FPGA debug

Tcl scripts and managing messages in ASIC & FPGA debug
by Don Dingee on 04-27-2016 at 4:00 pm

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More


Metric-Driven Verification for System Signoff

Metric-Driven Verification for System Signoff
by Bernard Murphy on 04-27-2016 at 12:00 pm

Everyone knows that verification is hard and is consuming an increasing percentage of verification time and effort. And everyone should know that system-level verification (SoC plus at least some software and maybe models for other components on a board) is even harder—which is why you see hand-wringing over how incompletely… Read More


No reason for FD-SOI Roadmap to follow Moore’s law!

No reason for FD-SOI Roadmap to follow Moore’s law!
by Eric Esteve on 04-26-2016 at 4:00 pm

We in Semiwiki are writing about FD-SOI since 2012, describing all the benefits offered by the technology in term of power consumption, price per performance compared with FinFET, etc. Let me assess again that I am fully convinced that FD-SOI is a very smart and efficient way to escape from the Moore’s law paradox: the transistor… Read More


SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar

SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar
by Bernard Murphy on 04-26-2016 at 12:00 pm

Fed up with ECOing your way out of test problems? You might want to register for this webinar.When you’re building monster SoC FPGAs, you have all the same problems you have with any other SoC. That includes getting to very high test coverage as quickly as you can with a design targeted to the most advanced processes. We’re not just … Read More


Stop the Dashboard Insanity!

Stop the Dashboard Insanity!
by Roger C. Lanctot on 04-26-2016 at 7:00 am

Speaking as part of the digital track at this week’s NAB confab, John Ellis proclaimed the demise of the dashboard radio in the coming world of automated vehicles. The headline reporting his talk in Tom Taylor’s newsletter was “Radio is on a path to extinction in the vehicle.”There’s no point in being subtle … Read More


Fast Track to a reconfigurable ASIC design

Fast Track to a reconfigurable ASIC design
by Don Dingee on 04-25-2016 at 4:00 pm

Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More


Would Sauron have made the One Ring if he had known about Plasmonics?

Would Sauron have made the One Ring if he had known about Plasmonics?
by Mitch Heins on 04-25-2016 at 7:00 am

In J.R.R. Tolkien’s novel ‘Lord of the Rings’, the Dark Lord Sauron created the “One Ring” as the ultimate weapon to conquer all of Middle-earth. So too it seems that in the world of integrated silicon photonics, the “ring” has become somewhat ubiquitous and powerful. Resonance … Read More