FPGA’s are the new superstar in the world of Machine Learning and Cloud Computing, and with new methods of implementing them in SOC’s there will be even more growth ahead. FPGA’s started out as a cost effective method for implementing logic without having to spin an ASIC or gate array. With the advent of the web and high performance… Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read More
Adding Expertise to GenAI: An Insightful Study on Fine-TuningI wrote earlier about how deep expertise, say…Read More
EDA Has a Value Capture Problem — An Outsider’s ViewBy Liyue Yan (lyan1@bu.edu) Fact 1: In the…Read More
WEBINAR: How PCIe Multistream Architecture is Enabling AI ConnectivityIn the race to power ever-larger AI models,…Read More
A Six-Minute Journey to Secure Chip Design with CaspiaHardware-level chip security has become an important topic…Read More
LETI Days 2017: FD-SOI, Sensors and Power to Sustain Auto and IoT
I have attended last week to the LETI Days in Grenoble, lasting two days to mark the 50[SUP]th[/SUP] anniversary of the CEA subsidiary. Attending to the LETI Days is always a rich experience: LETI is a research center counting about 3000 research engineers, but LETI is also a start-up nursery. The presentations are ranging from … Read More
Webinar: Synopsys on Clock Gating Verification with VC Formal
Clock gating is arguably the mostly widely-used design method to reduce power since it is broadly applicable even when more sophisticated methods like power islands are ruled out. But this style can be fraught with hazards even for careful designers. When you start with a proven-correct logic design and add clock gating, the logic… Read More
Open Source Hardware: Chiplicity.io
What’s new with eFabless? Let’s check in with CEO Michael Wishart (MSW) and CTO Mohamed Kassem CTO (MKK):… Read More
ADAS and Vision from Cadence
A huge theme at #54DAC this year was all things automotive and in particular the phrase ADAS (Assisted Driver Assistance Systems), so I followed up with Raja Tabet a corporate VP of emerging technology at Cadence. We met on Monday in a press room where I quickly learned that Cadence has been serving the automotive industry for the … Read More
Nvidia Handles Data, Senate with Care
When speaking before the U.S. Senate or Congress one has to choose one’s words carefully. The temptation, when one is speaking before legislators and microphones and cameras, is to tell it like it is and speak truth to power. The reality is that the power of the legislators and the microphones and the cameras must be respected and,… Read More
HW and SW Co-verification for Xilinx Zynq SoC FPGAs
It constantly amazes me at how much FGPA companies like Xilinx have done to bring ARM-based CPUs into a programmable SoC along with FPGA glue logic. Xilinx offers the Zynq 7000 and Zynq UltraScale+ SoCs to systems designers as a way to quickly get their ideas into the marketplace. A side effect of all this programability and flexibility… Read More
Capture the Light with Integrated Photonics
I wrote up a quick article in the weeks before the Design Automation Conference (DAC) letting readers know that Integrated Photonics were indeed coming to DAC again this year. As a follow up, I attended the DAC presentation, ‘Capture the Light. An Integrated Photonics Design Solution from Cadence, Lumerical and PhoeniX Software’,… Read More
Bosch to Build $1.1 Billion Fab for Automotive and IoT!
There has been quite a bit of coverage on this already but Bosch building a fab in Dresden is a big deal so let me share my experience, observation, and opinion as us bloggers do. The $1.1B question of course is: Why didn’t Bosch invest in GlobalFoundries FD-SOI fabs in Dresden instead? Automotive and IoT is perfect for FD-SOI,… Read More
3D NAND Myths and Realities
For many year 2D NAND drove lithography for the semiconductor industry with the smallest printed dimensions and yearly shrinks. As 2D NAND shrunk down to the mid-teens nodes, 16nm, 15nm and even 14nm, the cells became so small that there were only a few electrons in each cell and cross-talk issues made further shrinks very difficult… Read More
AI RTL Generation versus AI RTL Verification