Vivek Vishwakarma is an entrepreneur, investor, and technologist leading ThirdAI Automation, an industrial AI company that accelerates troubleshooting and reporting through automated root-cause analysis. A former technologist at Intel with 10+ patents and 300+ research citations, he speaks on the intersection of advanced… Read More
Broadcom Told the Truth. The Market Hasn’t Heard the Rest of It Yet.Hock Tan and his CFO Kirsten Spears logged…Read More
CEO Interview with Chuck Gershman of Owl Autonomous ImagingChuck Gershman is the CEO and co-founder of…Read More
CEO Interview with Daniel Schall of Black SemiconductorDr. Daniel Schall is CEO and Co-Founder of…Read More
Alchip Accelerates on AI ASIC DemandAlchip Technologies reported improved financial results for the…Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys ToolsAs advanced packaging becomes a critical enabler for…Read MorePodcast EP348: How Lemurian Labs is Building the Foundation for AI’s Next Era with Jay Dawani
Daniel is joined by Jay Dawani, co-founder and chief executive officer of Lemurian Labs, where he leads the company’s mission to reinvent AI infrastructure for greater efficiency, accessibility and performance. With a background spanning AI system architecture, hardware-software co-design and performance optimization,… Read More
The Hidden Cost of Using Claude for Documentation
Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.
Modern LLMs can generate… Read More
Re-Spins Get You Fired, Says Intel CEO Lip-Bu Tan
Intel CEO Lip-Bu Tan’s statement that “re-spins get you fired” reflects the enormous pressure facing semiconductor companies as chip complexity, manufacturing costs, and competitive demands continue to rise. In the semiconductor industry, a “re-spin” occurs when a chip design must be revised and manufactured again because… Read More
WEBINAR: Caspia’s AI Makes You a Security Verification Expert
Let’s face it, powerful, highly trained AI is making it easier to find security flaws in many systems. When the attack surface becomes the underlying hardware, the risks grow exponentially. Unlike software, hardware can’t easily be “patched”. Early, advanced security verification is the way to mitigate these risks, but doing… Read More
CFrame60: Rewriting the Rules of Frame Compression
Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality,… Read More
Quantum Simulation Using Decision Diagrams. Innovation in Verification
Quantum gate simulation complexity explodes as qubit counts increase. One way to manage this complexity in simulation on classical computers is through use of decision diagrams in place of matrices. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer… Read More
SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.
Indeed, for a complex SoC project, the number of possible configurations… Read More
Engineering the Next Era of Semiconductor Innovation
The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens,… Read More
SRAM compilers targeting automotive SoCs on advanced nodes
Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More


Disaggregating AI Compute to Break the Tokens Barrier