Demand Meets Design: RISC-V and the Next Wave of AI HardwareArtificial intelligence (AI) is transforming every layer of…Read More
The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology's Pivotal RoleRISC-V has emerged as a cornerstone of modern…Read More
GlobalFoundries, MIPS, and the Chiplet Race for AI DatacentersGlobalFoundries’ (GF) acquisition of MIPS in 2025 wasn’t…Read More
Moores Lab(AI): Agentic AI and the New Era of Semiconductor DesignFor decades, chip design has been a delicate…Read More
Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®In a landmark presentation at the 2025 IEEE…Read More
Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing… Read More
In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages … Read More
In the relentless race to power next-generation artificial intelligence (AI) systems, data connectivity has emerged as the critical bottleneck. As AI models balloon in size—from billions to trillions of parameters—compute resources alone are insufficient. According to Ayar Labs, approximately 70% of AI compute time is … Read More
At the AI Infra Summit 2025, Synopsys showed how artificial intelligence has become inseparable from the process of creating advanced silicon. The company’s message was clear: AI is an end-to-end engine that drives every phase of chip development. Three Synopsys leaders illustrated this from distinct vantage points. Godwin… Read More
Early last year we talked about state space models, a recent advance over large language modeling with some appealing advantages. In this blog we introduce neurosymbolic methods, another advance in foundation technologies, here applied to automated code generation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano… Read More
The TSMC Open Innovation Platform (OIP) Ecosystem Forum kicked off on September 24 in Santa Clara, CA. This is the event where TSMC recognizes and promotes the vast ecosystem the company has created. After watching this effort grow over the years, I feel that there is nothing the group can’t accomplish thanks to the alignment and… Read More
Synopsys has deepened its collaboration with TSMC certifying the Ansys portfolio of simulation and analysis tools for TSMC’s cutting-edge manufacturing processes including N3C, N3P, N2P, and A16. This partnership empowers chip designers to perform precise final checks on designs, targeting applications in AI acceleration,… Read More
For the so-called “2nm” node or beyond, the minimum metal pitch is expected to be 20 nm or even less, while at the same time, contacted gate pitch is being pushed to 40 nm [1]. Therefore, we expect via connections that can possibly be as narrow as 10 nm (Figure 1)! For this reason, it is natural to expect High-NA EUV lithography as the go-to
Jiadi Zhu is the CEO and founder of CDimension, a company rethinking chip design to shape the next generation of computing. Under his leadership, CDimension is creating the next generation of building blocks for chips, starting with materials and scaling up to full systems that can power everything from today’s AI and advanced… Read More
Daniel is joined by Dan Zheng, VP of Partnerships and Operations at Clockwork. Dan was the General Manager for Product and Partnerships at Urban Engines which was acquired by Google in 2016. He has also held roles at Stanford University and Google.
Dan explores the challenges of operating massive AI hardware infrastructure at … Read More
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Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools