Toshio Nakama is the founder and the CEO of S2C and also a strong advocate of FPGA accelerated ASIC/SoC design methodology. Mr. Nakama devotes much of his time in promoting scalable Prototyping/Emulation hardware architecture and defining automated software specifications. He first started his career at Altera in 1997 and … Read More





Upping the Safety Game Plan for Automotive SoCs
Thanks to advanced hardware and software, smart vehicles are improving with every generation. Capabilities that once seemed far-off and futuristic—from automatic braking to self-driving at the very pinnacle—are now either standard or within reach. However, considering how vehicle architectures have continued to evolve,… Read More
Architecture Wrinkles in Automotive AI: Unique Needs
Arteris IP recently spoke at the Spring Linley Processor Conference on April 21, 2021 about Automotive systems-on-chip (SoCs) architecture with artificial intelligence (AI)/machine learning (ML) and Functional Safety. Stefano Lorenzini presented a nice contrast between auto AI SoCs and those designed for datacenters.… Read More
Chip Design in the Cloud – Annapurna Labs and Altair
The above title refers to a webinar that was hosted by Altair on April 28th. Chip design in the cloud is not a new idea. So, what is the big deal with the above title. Sometimes titles don’t reveal the full story. Annapurna Labs happens to be an Amazon company. It used to be an independent semiconductor company that was acquired by Amazon… Read More
NetApp Simplifies Cloud Bursting EDA workloads
Why burst EDA workloads to the cloud
Time to market challenges are nothing new to those of us who have worked in the semiconductor industry. Each process node brings new opportunities s along with increasingly complex design challenges. 7nm, 5nm and 3nm process nodes have introduced scale, growth, and data challenges at a level… Read More
Extending Moore’s Law with 3D Heterogeneous Materials Integration
A great deal has been written of late about the demise of Moore’s Law. The increase in field-effect transistor density with successive process nodes has slowed from the 2X every 2 1/2 years pace of earlier generations. The economic nature of Moore’s comments 50 years ago has also been scrutinized – the reduction in cost per transistor… Read More
Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads
During the week of April 19th, Linley Group held its Spring Processor Conference 2021. The Linley Group has a reputation for convening excellent conferences. And this year’s spring conference was no exception. There were a number of very informative talks from various companies updating the audience on the latest research and… Read More
Webinar: Challenges in creating large High Performance Compute SoCs in advanced geometries
When we think about Compute and AI SoCs, we often focus on the huge numbers of calculations being carried out every second, and the ingenious IPs that are able to reach such high levels of performance. However, there also exists a significant challenge in keeping the vast quantities of data flowing around the chip which is solved … Read More
The Quest for Bugs: Bugs of Power
Shooting beyond the hill…
In former times (think WW1 before GPS and satellites), an artillery battery trying to shell targets out of sight behind a hill would have to rely on an approximate grid reference and a couple of soldiers on top of the hill (who could see the target) to tell them where the shots were landing. These range finders… Read More
What is a Data Lake?
“Data Lake” is a massive, easily accessible data repository for storing “big data”. Unlike traditional data warehouses, which are optimized for data analysis by storing only some attributes and dropping data below the level aggregation, a data lake is designed to retain all attributes, especially when you do… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet