Let me acknowledge up front that Avery isn’t the most visible EDA company around. If you know of them, you probably know their X-propagation simulator. Widely respected and used, satisfying a specialized need. They have also been quietly building over the years a stable of VIPs and happy customers, with a special focus on VIPs for… Read More





Safety Architecture Verification, ISO 26262
I love to read articles about autonomous vehicles and the eventual goal of reaching level 5, Full Automation, mostly because of the daunting engineering challenges in achieving this feat and all of the technology used in the process. The auto industry already has a defined safety requirements standard called ISO 26262, and one… Read More
WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?
Defacto SoC Compiler whose 9.0 release was announced recently automates the SoC design creation from the first project specifications. It covers register handling, IP and connectivity insertion at RTL, UPF and SDC file generation right to logic synthesis. As part of the generation process of RTL and design collaterals, basic… Read More
Supply Issues Limit 2021 Semiconductor Growth
Worldwide semiconductor shipments were $123.1 billion in 1Q 2021, up 3.6% from 4Q 2020 and up 17.8% from a year ago, according to WSTS. The 3.6% quarter-to-quarter growth was the highest for a first quarter since 1Q 2010, eleven years ago. The strong growth in 1Q21 implies strong growth in the following quarters and for the year 2021.… Read More
AMAT Nice Beat Strong Growth for Both 2021 & 2022
-Strong beat & guide- WFE up in 2021 & 2022-$160B combined
-Taking share in conductor etch & CVD
-Traditional Moore Scaling – No More?
-Foundry Logic leads followed by DRAM with weak NAND
Nice beat & guide & raise
Applied reported revenues of $5.58B with GM of 47.5% resulting in non-GAAP EPS of $1.63. … Read More
Podcast EP21: Leading Edge Analog Design
Dan is joined by Mark Williams, founder and CEO of Pulsic. The application of shape-based routing to automate analog design is explored. Pulsic’s revolutionary new automated analog layout system, Animate is also discussed. With this system, multiple, high quality, fully routed layouts can be created in minutes from … Read More
CEO Interview: Toshio Nakama of S2C EDA
Toshio Nakama is the founder and the CEO of S2C and also a strong advocate of FPGA accelerated ASIC/SoC design methodology. Mr. Nakama devotes much of his time in promoting scalable Prototyping/Emulation hardware architecture and defining automated software specifications. He first started his career at Altera in 1997 and … Read More
Upping the Safety Game Plan for Automotive SoCs
Thanks to advanced hardware and software, smart vehicles are improving with every generation. Capabilities that once seemed far-off and futuristic—from automatic braking to self-driving at the very pinnacle—are now either standard or within reach. However, considering how vehicle architectures have continued to evolve,… Read More
Architecture Wrinkles in Automotive AI: Unique Needs
Arteris IP recently spoke at the Spring Linley Processor Conference on April 21, 2021 about Automotive systems-on-chip (SoCs) architecture with artificial intelligence (AI)/machine learning (ML) and Functional Safety. Stefano Lorenzini presented a nice contrast between auto AI SoCs and those designed for datacenters.… Read More
Chip Design in the Cloud – Annapurna Labs and Altair
The above title refers to a webinar that was hosted by Altair on April 28th. Chip design in the cloud is not a new idea. So, what is the big deal with the above title. Sometimes titles don’t reveal the full story. Annapurna Labs happens to be an Amazon company. It used to be an independent semiconductor company that was acquired by Amazon… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet