Safety is a complex topic, but we’re busy. We take the course, get the certificate. Check, along with a million other things we need to do. But maybe it’s not quite that simple. I talked recently with Kurt Shuler (VP of marketing) and Stefano Lorenzini (functional safety manager) at Arteris IP and concluded that finding enlightenment… Read More





Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks
The move to true 3D IC, monolithic 3D SOC and 3D heterogeneous integration may require one of the most major design tool architecture overhauls since IC design tools were first developed. While we have been taking steps toward 3DIC with 2.5D designs with interposers, HBM, etc., the fundamental tools and flows remain intact in many… Read More
VLSI Technology Symposium – Imec Forksheet
FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.
At the … Read More
IPnest Forecast Interface IP Category Growth to $2.5B in 2025
Why should the interface IP category see such a high growth rate until 2025? IP vendors revenues totaled $1068 million in 2020, compared with $872 in 2019. That is 22.4% YoY growth rate and confirm that last year YoY value of 18% was the sign for a long-term growth, as IPnest shows in “Interface IP Survey 2016-2020 & Forecast 2021-2025”,… Read More
On Standards and Open-Sourcing. Verification Talks
At Veriest we host VERIFICATION MEETUPS periodically to share verification wisdom. In our virtual meetings we’ve had hundreds of attendants from the US, Europe, Israel, India, and China. Most recently we were able to host a live event in Israel – I want to share feedback from that meeting.
We started with two presentations:… Read More
The Quest for Bugs: “Correct by Design!”
In this article we take an objective view of Virtual Prototyping from the engineering lens and the “quest to find bugs”. In this instance we discuss the avoidance of bugs in terms of architecting complex ASICs to be “correct by design”.
AI Challenges
It is not surprising to find out that other areas of human endeavour, beyond semiconductor… Read More
Podcast EP27: Veriest and its role in the semiconductor ecosystem
VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More
Resist Development for High-NA EUV
The successful transition to a new fabrication process from development to high volume manufacturing requires a collective, collaborative effort among process engineers, equipment manufacturers, and especially, chemical suppliers. Of particular importance is the chemistry of the photoresist materials and their interaction… Read More
Achieving Scalability Means No More Silos
This is a story of contrasts and counter-intuitive results. Perforce recently published a white paper discussing enterprise scalability – what it takes, why it’s important and what can get in the way. The discussion will shake up some long-held notions regarding effective project management. The results can be significant,… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet