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Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street
by Robert Maire on 07-02-2022 at 10:00 am

Stock Crash 2022

-Micron reports weak outlook for fiscal Q4
-2023 capex to be down versus 2022 capex of $12B & Q3’s $2B
-Company keeping inventory off street to support pricing
-Memory is usually the first shoe to drop in a down cycle

Sharp drop in demand at end of Q3…..

Micron reported a sharp drop in demand at the end of its fiscal Q3,… Read More


Semiconductor Hard or Soft Landing? CHIPS Act?

Semiconductor Hard or Soft Landing? CHIPS Act?
by Robert Maire on 07-02-2022 at 6:00 am

Off the cliff without skidmarks

-Chip cycle will come down. Only question is landing impact
-What does cyclical end do to re-shoring & build out plans?
-Is it less demand, excess supply or both? Does it matter?
-CHIP Act rescue efforts get desperate switching to threats

Any landing you can walk away from is a good one

For those of us who have been in the semiconductor… Read More


Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
by Daniel Nenni on 07-01-2022 at 10:00 am

Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel, Blackstone,… Read More


The Lines Are Blurring Between System and Silicon. You’re Not Ready.

The Lines Are Blurring Between System and Silicon. You’re Not Ready.
by Daniel Nenni on 07-01-2022 at 8:00 am

3D Memory HBM Ansys

3D-ICs bring together multiple silicon dies into a single package that’s significantly larger and complex than traditional systems on a chip (SoCs). There’s no doubt these innovative designs are revolutionizing the semiconductor industry.

3D-ICs offer a variety of performance advantages over traditional SoCs. Because … Read More


Cadence Execs Look to the Future

Cadence Execs Look to the Future
by Dave Bursky on 07-01-2022 at 6:00 am

CDNLive 2020

Everything is becoming digital, and everything digital requires semiconductors. Cadence’s President and CEO, Dr. Anirudh Devgan, highlighted this at the recent CadenceLIVE user conference and discussed many of the company’s accomplishments and future directions. Dr. Devgan also sees the emergence of data—especially … Read More


Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson

Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson
by Daniel Nenni on 06-30-2022 at 10:00 am

Dan is joined by Barry Paterson, Agile Analog’s new CEO. Barry has held senior leadership, engineering and product management roles at Wolfson Microelectronics and Dialog Semiconductor. He has been involved in the development of custom mixed-signal silicon solutions for many of the leading mobile and consumer electronics… Read More


Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More


Using an IDE to Accelerate Hardware Language Learning

Using an IDE to Accelerate Hardware Language Learning
by Daniel Nenni on 06-29-2022 at 10:00 am

Indian Institute of Technology IIT Bhubaneswar

Recently, in one of my regular check-ins with AMIQ EDA, I was pleased that they linked me up with an active customer. The resulting post summarized my discussion with three engineers from Kepler Communications Inc. They talked about using one of the AMIQ EDA products in the design of FPGAs for space-borne Internet connectivity.… Read More


Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am

Innovation New

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More


Intel Foundry Services Puts PDKs in the Cloud

Intel Foundry Services Puts PDKs in the Cloud
by Daniel Nenni on 06-28-2022 at 10:00 am

Intel Foundry Services Roadmap

Intel announced today that they are partnering with cloud and EDA companies to better enable their foundry business. This is a natural extension of the Accelerator ecosystem program announced earlier. More and more chip designs are being done in the cloud and from my experience cloud based designs are better. Some companies use… Read More