I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software… Read More





What does the Lattice rejection mean for chip M&A?
Although the rejection of the Lattice deal was expected, it none the less has an impact on a number of dynamics in the chip industry and further M&A and consolidation. Freezing out China removes a “catalyst” in the market which help bid up values and add fear to both potential targets or those left out. Cross border… Read More
ATopTech is Back!
One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More
Burning Man 2017 – My vacation is your worst nightmare
I often use this space to report on industry events I have attended and what I have learned at them. So, this article will be a slight, but not complete, departure from this. I am reporting on my experiences at Burning Man this year. For the unacquainted, Burning Man is a temporary city of around 70,000 people in a remote desert-like … Read More
Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs
In automotive applications, advanced FinFET processes are great for high levels of integration and low power. But they also present some new challenges in reliability signoff. Ansys will be hosting a webinar to highlight the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge… Read More
High-Level Synthesis for Automotive SoCs
Some of the world’s most complex Systems-on-Chip (SoCs) are being developed for automotive applications. These SoCs have heterogeneous architectures with a variety of processors and accelerators that do real-time image processing for assisted and autonomous driving applications. The Bosch Visiontec team, in Sophia Antipolis,… Read More
Power Integrity from 3DIC to Board
The semiconductor industry has built decades of success on hyper-integration to increase functionality and performance while also reducing system cost. But the standard way to do this, to jam more and more functionality onto a single die, breaks down when some of the functions you want to integrate are built in different processes.… Read More
TSMC OIP and the Insatiable Computing Trend!
This year’s OIP was much more lighthearted than I remember which is understandable. TSMC is executing flawlessly, delivering new process technology every year. Last year’s opening speaker, David Keller, used the phrase “Celebrate the way we collaborate” which served as the theme for the conference. This year David’s… Read More
Semiconductor Device Physics, Lab in a Box
One of my favorite classes in college was the lab exercise, mostly because we actually got to use real electronics and then measure something, finally writing it up in our lab notebooks. The issue today is that a college student taking Electrical Engineering probably doesn’t have much access to 10nm FinFET silicon for use… Read More
Webinar Preview: Alexa, can you help me build a better SoC?
Nothing is pushing complexity in system-on-chips (SoCs) designs like the drive (no pun intended) to make autonomous vehicles a widespread reality. Autonomous vehicle systems require heterogeneous architectures with reliable, efficient communications between CPU clusters, vision processing accelerators, storage and… Read More
Should the US Government Invest in Intel?