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Lithography
Posted on by Fred Chen

Stitched Multi-Patterning for Minimum Pitch Metal in DRAM Periphery

Stitched Multi-Patterning for Minimum Pitch Metal in DRAM Periphery
by Fred Chen on 04-08-2025 at 6:00 am
Categories: Lithography

Key Takeaways

  • In a DRAM chip, memory array features are densely packed but lose regularity outside the array.
  • Pitch uniformity can be achieved through layout splitting for double patterning with stitching.
  • For minimum pitches above 40 nm, double patterning is sufficient; triple patterning may be used for lower pitches.
  • Triple patterning can replace quadruple patterning for minimum line pitches under 40 nm.
  • Stitched double patterning has been the standard approach for DRAM periphery metal patterning for a long time.

In a DRAM chip, the memory array contains features which are the most densely packed, but at least they are regularly arranged. Outside the array, the regularity is lost, but in the most difficult cases, the pitches can still be comparable with those within the array, though generally larger. Such features include the lowest metal lines in the periphery for the sense amplifier (SA) and sub-wordline driver (SWD) circuits.

A key challenge is that these lines are meandering in appearance, and the pitch is varying over a range; the local max/min pitch ratio can range from ~1.4 to 2. These pitches have different focus windows [1], and in EUV lithography, these windows may be separated by more than the resist thickness [2].

Pitch uniformity within a single exposure can be attained if the layout is split accordingly for double patterning with stitching [3,4] (Figure 1). The layout is dissected into stripes of alternating color, each color assigned to one of two exposures. Features may cross stripe boundaries; in that case, the two exposures need to stitch correctly at the boundaries.

Figure 1. Splitting a metal layout for stitched double patterning for better pitch uniformity.
Figure 1. Splitting a metal layout for stitched double patterning for better pitch uniformity.

Alternatively, some features like diagonals may be forbidden to be stitched, resulting in a different layout split (Figure 2).

Figure 2. Alternatively splitting the layout of Figure 1
Figure 2. Alternatively splitting a metal layout for stitched double patterning for better pitch uniformity, avoiding stitching of diagonal features.

For minimum pitches above 40 nm, we expect double patterning to be sufficient with ArF immersion lithography. In case the minimum pitch is lower than this, triple patterning may be used (Figure 3) with ArF immersion lithography, as an alternative to EUV double patterning.

Figure 3. Splitting the layout of Figure 1 for triple patterning
Figure 3. Parsing the layout of Figure 1 for triple patterning including stitching.

Previously, quadruple patterning was suggested for where the minimum line pitch is less than 40 nm [1], but it turns out triple patterning may suffice (Figure 4).

Figure 4. A quadruple patterning arrangement
Figure 4. A quadruple patterning arrangement [1] (left) can be rearranged to support triple patterning with stitching (center) or possibly even avoid stitching (right).
In some special cases, a multiple spacer approach may be able to produce the periphery metal pattern with islands and bends with only one mask exposure [5]. However, the stitched double patterning has been the default choice for a very long time [3,4]; it should be expected to kept that way for as long as possible, even through the mid-teen nm DRAM nodes [6].

References

[1] F. Chen, Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM.

[2] A. Erdmann et al., J. Micro/Nanolith. MEMS MOEMS 15, 021205 (2016); E. van Setten et al., 2012 International Symposium on EUV Lithography.

[3] Y. Kohira et al., Proc. SPIE 9053, 90530T (2014).

[4] S-Min Kim et al., Proc. SPIE 6520, 65200H (2007).

[5] F. Chen, Triple Spacer Patterning for DRAM Periphery Metal.

[6] C-M. Lim, Proc. SPIE 11854, 118540W (2021).

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Also Read:

A Perfect Storm for EUV Lithography

Variable Cell Height Track Pitch Scaling Beyond Lithography

A Realistic Electron Blur Function Shape for EUV Resist Modeling

Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution

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