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Senior Staff Engineer, DDR and IP RTL

Senior Staff Engineer, DDR and IP RTL
by Admin on 03-24-2020 at 6:57 am

Website Achronix

Primary Responsibilities:

The employee will be responsible for block-level IP RTL design as well as full chip-level integration RTL design for Achronix’s FPGA products. The employee is expected to take independent ownership of complex design challenges, which may include:

  • Micro-architecture development
  • RTL code development
  • Timing constraints development with STA team
  • Performance modeling
  • Post-Si bring-up
  • Third-party IP analysis and integration
  • System-level reference design creation
  • Automation development for FPGA specific IP generation

The employee is also expected to participate regularly in interactions with global teams spanning System Engineering, Software, and Product Engineering.


  • Expertise in micro-architecture development and RTL coding
  • Hands-on experience at the implementation of DDR PHY/Controller with a strong understanding of the die-level and board-level protocol as well as design requirements is a must. Should be able to validate third-party IP for performance/area and SoC integration
  • Automation and scripting experience
  • Excellent verbal and written communication skills
  • Ability to work in a dynamic and fast-paced environment with a proactive mindset
  • Strong knowledge of Network protocols (PCIE or Ethernet) is a big plus
  • Hands-on experience in integrating/Validating System interconnect (AXI interconnect) is a plus
  • Experience with system level performance modeling is a plus
  • Experience with post-Si bring-up and debug is a plus
  • Experience with synthesis and STA is a plus


  • Preferred BS/MS and 9+ years of experience in RTL design and verification
  • Previous experience in at least 3-4 product developments, including post-Si bring-up
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