Physical Design Engineer

Job Responsibilities

The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, APR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. Candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements.

Job Qualifications

1. Bachelor’s or Master’s degree in EE or CE with 4+ years’ relevant working experience.
2. Good English speaking and writing capability.
3. Expertise in Cadence Innovus and/or Synopsys ICC2.
4. Experience in block level place and route implementation with multi-voltage & multi-corner designs.
5. In-depth understanding of place and route flow.
6. Knowledge of lower power design.
7. Experience in advanced technology nodes is a plus.
8. Timing closure and power analysis skills.
9. Hands on experiences in layout verification and DRC fixes.
10. Good coding skills in TCL.
11. Good interpersonal and communication skills.
12. Self-motivated and excellent team spirit.