[Military Service Exemption] RTL Design Engineer

Job Responsibilities

• Module development including spec definition, macro/micro architecture design, RTL coding, simulation, and synthesis

• Use scripting tools to maintain and enhance existing RTL blocks and verification environments

• Collaborate with the software development team

Essential requirements

• ASIC/SOC/FPGA development experience

• Expertise in design and verification using Verilog HDL and C/C+

• Knowledge of AMBA AXI and the memory subsystem

• Possesses technical skills in EDA tools for RTL simulation, debugging, synthesis, and lint/CDC

Benefits

• Python/Perl users

• Those capable of using SystemVerilog test bench

Working environment and welfare

• Flexible working hours (Core time 11:30 ~ 15:30)

• Lunch/Dinner Support

• Provides 3 million won in optional employee benefits per year

• Refreshment vacation and vacation allowance

• Annual health checkups worth 700,000 won provided

• Support for enhancing development capabilities, such as promoting in-house seminars

• Use an English nickname

• Starting annual salary of 50 million won for a bachelor’s degree

Note

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• This recruitment is for those eligible for military service exemption (specialized research personnel).