[Daegu] RTL Design Engineer

Job Responsibilities

• Module development including video spec definition, macro/micro architecture design, RTL coding, simulation, and synthesis

• Use scripting tools to maintain and enhance existing RTL blocks and verification environments

Essential requirements

• Experience in hardware design using Verilog RTL

• Expertise in design and verification using Verilog HDL and C/C++

• Possesses technical skills in EDA tools for RTL simulation, debugging, synthesis, and lint/CDC

Benefits

• Users capable of using Python/Linux scripts

• Verification experience using FPGA platforms

Working environment and welfare
• Flexible working hours (Core time 11:30 ~ 15:30)

• Lunch/Dinner Support

• Provides 3 million won in optional employee benefits per year

• Refreshment vacation and vacation allowance

• Annual health checkups worth 700,000 won provided

• Support for enhancing development capabilities, such as promoting in-house seminars

• Use an English nickname

• Starting annual salary of 50 million won for a bachelor’s degree

Note

• Recruitment Process: Document Screening > RTL Test > Interview > Final Acceptance (*The practical test may be omitted depending on the circumstances)

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• If the information in your resume is found to be false, your employment may be cancelled.