Design Verification Engineer H/F

Arteris enables engineering and design teams at the world’s most innovative companies to connect and integrate the system-on-chips (SoCs) that power today’s and tomorrow’s technological transformations.

If you’ve held a smartphone, driven an electric car, or powered up a smart TV, you’ve already come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or operating in the cloud within a data center.

Your Role as a Design Verification Engineer at Arteris

We are looking for a Design Verification Engineer to join our teams and work on the most advanced SoC and HSI assembly flows.

In this role, you will have a direct impact on the development environment, architecture, verification, and all associated processes. You will actively contribute to ensuring the quality and robustness of the tools and deliverables related to Arteris’ Register Bank Compiler.

Key Responsibilities

• Define, document, develop, and execute simulation-based verification tests for Arteris’ Register Bank Compiler tool, compatible with RTL simulators (Cadence, Synopsys, Siemens)
• Develop a Python framework for the automatic generation of SystemVerilog and/or UVM test benches
• Maintain and enhance tests within the continuous integration flow, refine metrics, and increase automation
• Contribute to the improvement of processes, methodologies, and performance indicators
• Use modern documentation, specification, and project tracking tools (Confluence, Jira)
• Collaborate with developers to identify EDA-specific testing requirements
• Participate in code reviews and unit testing with other developers to ensure code quality

What You Bring

• 7+ years of experience as an RTL Verification Engineer
• Strong expertise in the UVM framework
• Knowledge of RTL languages (VHDL, Verilog, SystemVerilog)
• Proficiency in Python
• Excellent written and verbal communication skills in English
• Curiosity, autonomy, rigor, results-driven mindset, and strong commitment to quality
• Strong knowledge of Python and object-oriented programming in general

Nice to Have

• Knowledge of the IP-XACT standard
• Knowledge of C-HAL
• Experience with equivalence checking tools
• Proficiency in French

Education Requirements

Engineering degree or equivalent (Computer Science, Electronics, or related field)

Estimated Compensation

€55,000 to €70,000 gross per year, depending on experience.
Your base salary will be determined based on your experience and the pay of employees in similar positions.

About Arteris

Arteris is a global leader in system IP used in semiconductors to accelerate SoC development. Its Network-on-Chip (NoC) interconnect technology and SoC integration automation solutions improve performance, reduce power consumption, and accelerate time-to-market.

With over 250 employees worldwide and headquarters in Silicon Valley, Arteris is a catalyst for SoC innovation for startups and global technology leaders alike.