Report To: VP, Chiplet Integration Design Solution Division
Development of effective heterogeneous chiplet integration design solutions for TSMC advanced semiconductor and packaging technologies to accelerate customers’ system design innovations and successes
- Research and development of effective heterogeneous chiplet integration design methodology and solutions
- System/Design/Technology Co-Optimization (SDTCO) for Performance, Power, Area, and Cost (PPAC)
- Electronic Design Automation (EDA) tools enablement and certification
- Customer’s design flow support
- M.S. degree or above in Electrical Engineering, Computer Science, Mechanical Engineering, Physics, Mathematics, Applied Physics, Applied Math
- Minimum of 3+ years of working experience in advanced semiconductor/packaging technologies or related fields
- Solid understanding of key principles behind computer simulation tools to build the model, simulate and analyze the results of timing analysis, signal integrity analysis, power integrity analysis, and thermal analysis of chiplet systems
- Working knowledge of Circuit simulation, High Frequency simulation, IR/EM simulation, Thermal simulation tools (such as HSPICE, Spectre, RedHawk, Voltus, FloTHERM, HFSS, …)
- Familiar with Advanced Placement and Routing (APR) tools (such as Cadence Innovus and Synopsys IC Compiler) and PPA analysis/optimization methodology
- Capabilities in design flow development and customer’s design flow support
- Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
- Personal Attributes
- Team player with good communication skills, responsibility & flexibility.
- Strong skills to go into technical details to find flow solutions for customers
Apply for job
To view the job application please visit tsmc.taleo.net.