Die-to-Die Interconnects using Bunch of Wires (BoW)

Chiplets are a popular and trending topic in the semiconductor trade press, and I read about  SoC disaggregation at shows like ISSCC, Hot Chips, DAC and others. Once an SoC is disaggregated, the next challenge is deciding on the die-to-die interconnect approach. The Open Compute Project (OCP) started 10 years ago as a way to share designs of data center products between a diverse set of companies, like: ARM, Meta, IBM, Intel, Google, Microsoft, Dell, NVIDIA, HP Enterprise, Lenovo and others. In July the OCP Foundation announced their approach to SoC disaggregation with an interface specification, and dubbed it Bunch of Wires (BoW).

I contacted Elad Alon, CEO and co-founder of Blue Cheetah Analog Design to learn about BoW and how it compared to the UCIe approach. Here’s a quick comparison:

• BoW
  • Focused on die disaggregation
  • Open standard from the start
  • Allows design freedom and application-specific optimization
• UCIe
  • Focused on package aggregation
  • Interoperability favored over design freedom, similar to PCIe
  • Specified by Intel, then other members added

In a package aggregation approach, there would’ve been separate chips to begin with, but now the chiplets are brought into the same package, almost a PCB-type thinking. With die disaggregation, all of the chiplet functions would’ve been combined in a single SoC, but the die size was too large or too costly. There’s room for both the BoW and UCIe approaches as chiplet use expands.

Bunch of Wires

The BoW is a open PHY specification for die-to-die (D2D) parallel interfaces that can be implemented in organic laminate or advanced packaging technologies. Here’s a diagram of what it looks like, along with some metrics:

With BoW the D2D interfaces can be optimized to the host chiplet products, using minimal required features while supporting interoperability. A slice for BoW contains 16 data wires, a source-synchronous differential clock, and two optional signals – FEC (error control), AUX (DBI, repair, control).

A stack is a group of slices extending towards the inside of the chiplet, then a link is one or more slices forming a logical interface from one chiplet to another.

In the BoW specification it only requires the wire order on the package, but not a specific bump map, giving you some flexibility while retaining interoperability. All of the PHYs must support 0.75V for compatibility across a wide range of process technologies, although systems can use other voltages to optimize for performance, BER or reach.

BoW Adoption

A version 1.0 specification was formally approved and released in July 2022, and an ecosystem has already formed as BoW is being designed into products using multiple process nodes: 65nm, 22nm, 16nm, 12nm, 6nm, 5nm.

Companies using or supporting BoW:

• Blue Cheetah Analog Design
• eTopus and QuickLogic  – eFPGA Chiplet template
• Samsung – foundry
• NXP – BoW PHY design
• Keysight – test and measurement
• Ventana Micro Systems
• DreamBig  – hyperscale Smart NIC/DPU chiplet
• d-Matrix – AI compute platform
• Netronome – SmartNIC

Both Blue Cheetah and d-Matrix have taped out with Bunch of Wire test chips, so we could expect silicon results later this year. You can even get involved with the weekly meetings, or start by reading the 33 page specification. BoW is an open specification, so there’s no NDA to sign or legal paperwork.

There is an OCP Global Summit, scheduled for October 18-20, and there’s an ODSA session on BoW.

Summary

Chiplet-based electronic systems are quickly emerging by semiconductor companies from around the globe, so it’s an exciting time to see emerging chiplet interconnect standards arrive to provide some standardization. The Open Compute Project has good momentum with version 1.0 of the BoW specification, and you can expect to see more news as companies announce products that use this interconnect later this year.

There’s even a “plugfest” for BoW PHY interoperability testing, and the interoperability community has several participants: Google, Cisco, Arm, Meta, JCET, d-Matrix, Blue Cheetah, Analog Port.

Related Blogs

• Analog Design Acceleration for Chiplet Interface IP
• Blue Cheetah Technology Catalyzes Chiplet Ecosystem