There are many reasons today for dividing up large monolithic SoCs into chiplets that are connected together inside a single package. Let’s look at just some of these reasons. Many SoCs share a common processing core with application specific interfaces and specialized processing engines. Using chiplets would mean that it is easier to reuse the main processing core and ancillary blocks to easily build special purpose IC’s for various markets. Mixing analog and digital functions on a single die can be difficult, especially at more advanced nodes. It would be more cost effective and simpler to build separate analog chiplets and interface them with digital die. Yield is also an issue. The larger a die is the more likely it is that there can be a defect or fabrication failure. This is especially painful when the entire chip has to be rejected. A failed chiplet can be discarded easily without adversely affecting the other parts of a large chiplet based IC design. The list of advantages goes on, but I think you get the idea.
Of course, chiplet based designs introduce new requirements and have some drawbacks. However, it has been pointed out that Gordon Moore saw the potential advantages of this approach back in 1964 when he said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” I recently saw this quote in a presentation from DAC by Intel, CHIPS Alliance and Blue Cheetah. The first issue that needs to be dealt with to make chiplets effective and practical is providing a method for interfacing them to each other.
To address this need, CHIPS Alliance developed the Advanced Interface Bus (AIB), which offers a standardized high bandwidth interface between chiplets. It uses wide parallel connections with dense microbump arrays. It can work at modest clock rates and can transfer massive amounts of data. The topic of AIB and its features is a whole other discussion from the DAC presentation. What Intel, Blue Cheetah and the CHIPS Alliance wanted to talk about is how to rapidly implement the analog AIB PHY for each technology node used in all the chiplets found in a design.
So-to-speak, this is where the rubber meets the road. When dividing up monolithic SoC’s into chiplets each one will need to have an AIB PHY implemented as an analog block – which is traditionally a difficult and time-consuming specialized design task. This is where Blue Cheetah comes in. They have been extending the BAG Framework, initially developed at UC Berkeley, to create generators for producing fully automated analog designs, from schematics and layouts to test benches, LEFs, LIBs, and behavioral models. While not all their generators are open source, the AIB PHY is freely available on GitHub. The BAG framework is also open source, making this a revolutionary proposition.
We are accustomed to open source software and development libraries and even tools. However, in the world of hardware design, open source has been a long time coming. Though recently we have seen the emergence of RISC-V providing an open source processor ISA. From the looks of it Blue Cheetah and BAG technology will change how we think of analog blocks in terms of reuse and retargeting. Adding to that the notion of open source generators for blocks that are needed to catalyze innovations, it seems that things are about to get very interesting.
Of course, not all of the generators that run in the Blue Cheetah offering are open source. This makes it useful for companies that want the advantages of generators without having to surrender rights to them. Blue Cheetah can even help with this internal development. There is a lot to digest here, and even more in the details of the AIB PHY generator operation and capabilities offered in the presentation. A key point is that this is not just layout generation. Rather, the AIB custom block generator is configurable and produces signoff quality schematics and layouts along with industry standard integration views.
The layout flow is equally sophisticated. The BAG API lets the generator developer specify a high level floorplan, which can be used to produce designs across may target technologies and parameters.
The test vehicle for the AIB PHY using BAG has already been delivered and tested. It was a 2-channel test chip taped out on Intel 22FFL in January 2020. The silicon met the required specifications, showing zero error loopback results at 2Gbps.
Clearly the Blue Cheetah Ecosystem is very helpful for designers who are dividing up large monolithic SoCs into chiplets. The presentation points to the RTL and the generator for the AIB PHY on GitHub. The age of chiplets has arrived, leading to new kinds of designs and further innovation. While generator development requires expertise, once they are implemented a larger community of developers can leverage them to boost productivity. This is no different from how open source works. Next we can look forward to AIB 2.0, which will offer improved bandwidth and density.