Heterogeneous Processing: Power Reduction and Performance Advances

Implementation of Heterogeneous processors has shown demonstrated reduction in power consumption and improved performance in mobile processors like ARM_big.LITTLE technology, where low power and relatively slower cores are coupled with the more powerful ARM cores. According to ARM Holdings, it can save 75% of CPU energy in low to moderate performance scenarios, and can increase performance by 40% in high performance scenarios. Due to its power efficient characteristics, it is present in applications of heterogeneous computing and many high end mobile processors also follow ARM big.LITTLE.

Currently, many desktop and mobile processors have heterogeneous computing with the CPU and GPU on the same integrated circuit. Present day AMD’s APU and Intel Laptop processor uses Heterogeneous System Architecture (HSA) which enables it to have a CPU and GPU on a single die. A step towards Heterogeneous-ISA is AMD’s Sky Bridge project. Sky Bridge attempts to integrate circuitry between two systems on a chip (SoC). This architecture has two separate instruction sets on one chip; however, problems arise when attempting to integrate these two chips into one integrated circuit design – mainly communicating between each instruction set and chipset circuit design. This should reduce hardware and software costs without cluttering the computer. “Different motherboards are currently required for x86 and ARM chips, and it’s expensive for developers and users alike to support disparate architectures, said Lisa Su, general manager of AMD’s global business units, during a press event that was webcast.” (Computer World article)

AMD recently came up with their first ARM server processor, AMD Opteron A1100 which is a step towards the Project Sky Bridge and in 2015 a lower power version would be compatible with another x86 CPU. According to AMD, they are developing their own ARM processing core called K12 scheduled for release in 2016.

Multiple Instruction Set Architecture’s in Chip Level Multiprocessing need sufficient diversity to be useful for heterogeneous processing. Modern Instruction Set Architectures (e.g. ARM, x86 and x64, MIPS, Raspberry PI) have enough diversity between themselves to provide an acceptable increase in efficiency and decrease in power consumption to effectively fund the research for heterogeneous processing. There are four key elements to heterogeneous processing: code density, dynamic instruction count, register pressure, and floating-point & SIMD support.

Code density refers to the efficiency of the cache, memory use, and power consumed by interchanging between instruction set architectures that use different bit lengths. Dynamic instructions count refers to the number of the lines of code needed to be encoded and decoded by a multi instruction set architecture multiprocessor. Because of the differences inherent in multiple ISAs, either more or less lines of code are needed to carry out parallel processing on the same code. Register pressure refers to the different ways each ISA uses the registers. Because some ISAs use the registers specifically, different implementations must be used to correctly allocate instructions passed through the registers; software emulation of registers and direct memory addressing are some of the methods used to reduce register pressure. The final key element of heterogeneous computing is floating-point and SIMD support. Lightweight ISAs sometimes forgo precise floating-point and single instruction multiple data support in favor of lower power consumption, producing a convergence of ISA activity, and creating a convergence of operations where (in an ideal situation) asymptotic divergence should occur.

Core switching can be used as an advantage. certain code can be best for one processor but will often not be the best for another. So, with different cores on a chip we can switch the cores according to their efficiencies. Moreover, in heterogeneous computing we can shut down the other core instead of making it idle; there would be no static leakage and dynamic switching power which will enable a system to be power efficient as a result. Since core switching costs time, it also acts as a disadvantage.

Designing the scheduler according to the heterogeneous chip can prove efficient. The way of arranging processor cores also affect the performance. In present day, ARM*_big.LITTLE has three ways of arranging the scheduler which has different advantages depending on the arrangement. Similarly, differing arrangements can prove to be a positive performance factor in a heterogeneous processors and can utilizes each processor to its max.

Future applications of heterogeneous computing can include multi-ISA processors. Different architectures are both good and bad at different aspects: while multi-ISA heterogeneous computing can enable a processor to be more efficient, a single-ISA processor outperforms the former. For example: ARM processors are known for their low power requirement and x86 are known for faster processing. In multi-ISA we can combine ARM and x86 core that could prove to be better for processing. Some big companies are currently working on it but there are a lot of challenges. Heterogeneous computing has challenges with applications like binary interface, which includes endianness, calling conventions, and memory layout. All of this depends on both the architecture and compiler being used.

Heterogeneous designs, if properly implemented, can maximize efficiency, though there are many challenges with the designs, such as compatibility of software with the specific compiler that connects each instruction set architecture. If the solutions to these problems can be overcome, future processors can effectively provide advancement in computational architectures.

By Suprabh Singh and Thomas Pitts

The University of Mississippi Electrical Engineering Department introduced a Digital CMOS/VLSI Design course this semester. As part of this course, students researched a contemporary issue and wrote a blog article about their findings for presentation on SemiWiki. Your feedback is greatly appreciated.

References:
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen (2003). Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. 36[SUP]th[/SUP] International Symposium on Microarchitecture, IEEE.
Link: http://www.microarch.org/micro36/html/pdf/kumar-SingleISAHeterogen.pdf

Antonio Barbalace, Alastair Murray, Rob Lyerly, Binoy Ravindran (2013). Towards Operating System Support for Heterogeneous-ISA Platforms. The 4[SUP]th[/SUP] Workshop on Systems for future Multicore Architechture, University of Washington.
Link: http://sfma14.cs.washington.edu/wp-content/uploads/2013/03/sfma2014_submission_2.pdf

Ashish Venkat, Dean M. Tullsen (2014) Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor. Proceeding of the 41st annual international symposium on Computer architecuture.

Big.LITTLE Technology.
Link: http://www.arm.com/products/processors/technologies/biglittleprocessing.php

Agam Shah (May 5, 2014). AMD unites x86 and ARM in Project Skybridge. Computer World.com.
Link: http://www.computerworld.com/article/2489007/computer-processors/amd-unites-x86-and-arm-in-project-skybridge.html