ARM SoC Hardening

Last year at DACI discovered a physical IP company called DXCorrthat competed against giant ARM. This year the company has selected a different direction, so I got caught up with Nirmalya Ghosh, the CEO to hear about the changes.

Nirmalya Ghosh, DXCorr

Q: How is business for DXCorr?

A: It has been an awesome year for DXCorr. The company headcount stands at close to 60 now and we just moved to a shiny building in Bangalore.

Q: What is new this year for DXCorr at DAC?

A: We are slowly positioning ourselves as the best “ARM SoC hardening house in the world”.

Q: ARM is a popular architecture, how do you achieve good SoC hardening results?

A: We achieve this using our proprietary RTL level floorplanning tool called DXPROwhich seamlessly interfaces with mainstream EDA P&R toolset and with our very own Physical IP (memories, register files, CAMs, standard cells).

DXPRO – Placement and Routing Optimization Tool

Q: How is your design service different than what others can offer?

A: We strongly believe, the way we are handling the power-aware RTL placement, no one else is doing that.

Q: What kind of QoR can you achieve with your SoC hardening?

A: We believe we can save roughly save 20% of active power off an ARM SoC implementation this way.

Q: Where can people find you at DAC?

A: We’re in booth #733 this year.

DXCorr is a provider of leading edge physical IP solutions for advanced semiconductor process technologies. DXCorr’s products meet the needs of performance-oriented, low-power SOC designs and include advanced memory IP such as SRAMs, CAMs, multi-port memories and memory subsystems as well as differentiated standard cell solutions. DXCorr also provides PDK and PCELL development for analog and mixed-signal designs and RTL to GDS design services.

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