Andes RISC-V CON in Silicon Valley Overview

RISC-V conferences have been at full capacity and I expect this one will be well attended as well. Andes is the biggest name in RSIC-V. The most notable thing about RISC-V conferences is the content. Not only is the content deep, it is international from the top companies in the industry. It is hard to find a design win these days without RISC-V content, absolutely.

We did a podcast with Andes covering the conference: Podcast EP282: An Overview of Andes Focus on RISC-V and the Upcoming RISC-V CON

Registration: visit the event website

An additional keynote has been added:

Nvidia’s Frans Sijstermans (VP of Multimedia Architecture/ ASIC) will present  Use of RISC-V in NVIDIA’s Deep-Learning Accelerator.

This one should be a big draw in addition to the keynote from Andes co-founder, Chairman and CEO  Frankwell Lin “Celebrating 20 years of driving SIP innovation and 15 years of pioneering RISC-V”.

Here are the other keynotes:

– Charlie Su, President and CTO, Andes Technology – Provides insights on advancing modern computing with Andes RISC-V processor solutions.

– Paul Master, Co-founder and CTO, Cornami – Presenting Fully Homomorphic Encryption, the Holy Grail.

Fireside chat: What’s coming in AI? – Facilitated by Charlie Cheng, Andes, Board Advisor with keynotes from:

– Jeff Bier, Founder, Edge AI and Embedded Vision Alliance

– Pete Warden, Founder & CEO, Useful Sensors

There are two full tracks this year, the main conference track and a developer track. The developer track includes hands-on technical training:

Developer Track – Hands-on Technical Training (Limited Seats!)

Four in-depth, 1-hour sessions designed for engineers who want to dive deep into RISC-V technology. Bring your laptop fully charged!

• Optimization with RISC-V Vector ISA – Curious about RISC-V Vectors (RVV) but unsure how it works? This session covers the basics and how it boosts vector performance. You will get hands-on experience writing and running vector software using AndeSight tools on RVV-capable processors.
• IAR Professional Tools for RISC-V – Learn how professional tools can help you debug your application more quickly and efficiently, accelerating your time to market. Also, discover how prequalified Functional Safety tools can enhance your products.
• Create Your Own RISC-V Custom Instructions – Want to create your own RISC-V Instructions to accelerate your application? This session explores Andes’ Automated Custom Extensions (ACE) for enhancing the RISC-V ISA, with a hands-on demo using Andes Copilot, which automates much of the process.
• Unleashing the Power of Heterogeneous Computing: Building a complex SoC with high compute and memory demands? Avoid performance surprises by understanding how CPU and GPU subsystems interact under real workloads and memory hierarchies. This session demonstrates how trace-based simulation can uncover bottlenecks, validate compute and cache architecture decisions, and improve heterogeneous system performance.

I know quite a few of the presenters on the main conference track and I can tell you it is an all star cast. The main conference welcomes all attendees, featuring over ten sessions and speeches that cover the RISC-V market and the development of SoCs using RISC-V across AI, automotive, application processing, communications, and more. Participants will also have opportunities to network with speakers and exhibitors from over twenty sponsoring companies offering IP, software, tools, services, and products.

This really is an excellent networking event at one of my favorite Silicon Valley locations which includes breakfast, lunch and a networking reception.

Event Details:

– Location: DoubleTree by Hilton, San Jose, CA
– Time: 8:30 – 6:00 PDT
– Admission: RISC-V CON is free to attend
– Registration: visit the event website

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters.

With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X , and YouTube.

Also Read:

Webinar: Unlocking Next-Generation Performance for CNNs on RISC-V CPUs

Relationships with IP Vendors

Changing RISC-V Verification Requirements, Standardization, Infrastructure