Key Takeaways
- Mixel, Inc. will exhibit at DAC 2025, showcasing their MIPI PHY IP and LVDS IP.
- The company serves major semiconductor and system companies in mobile and adjacent applications.
- Mixel's MIPI IP can function as a transmitter, receiver, or universal configuration, featuring unique implementations.
- Mixel recently announced MIPI C-PHY/D-PHY combo IP with high aggregate bandwidth capabilities.
- Mixel has achieved ISO certifications for quality management and automotive functional safety.
Mixel, Inc., a leading provider of mixed-signal interface IP, will exhibit at booth #2616 at Design Automation Conference (DAC) 2025 on June 23-25. The company will demonstrate its latest customer demos featuring Mixel’s MIPI PHY IP and LVDS IP. Mixel’s customers include many of the world’s largest semiconductors and system companies targeting mobile and mobile-adjacent applications such as automotive, consumer/industrial IoT, VR/AR/MR, wearables, healthcare, and others.
At DAC, Mixel will be showcasing many MIPI customer demos who have integrated Mixel’s IP into their end product or SoC. One example is NXP, which leverages Mixel’s IP in multiple different applications. At DAC, Mixel will be showcasing an IoT application in the i.MX7ULP Applications Process featuring Mixel’s MIPI D-PHY DSI TX IP. This SoC is integrated into the Garmin Edge 830 Cycling GPS. Another MIPI D-PHY customer includes the Lattice Crosslink-NX low-power FPGA which features Mixel’s MIPI D-PHY Universal IP. Lattice FPGAs were announced to enable advanced driver experiences on Mazda Motor Corporation’s CX-60 and CX-90 models.
Mixel’s MIPI IP can be configured as a transmitter (TX), receiver (RX), or universal configuration which is the superset supporting both TX and RX in the same hard macro. Mixel also offers a unique MIPI implementation call TX+ and RX+. These proprietary MIPI IP configurations (patented in the case of RX+) allow for full-speed production testing without requiring a full MIPI Universal configuration, resulting in a substantial reduction in area and in standby power.
Mixel recently announced the availability of its latest MIPI C-PHY/D-PHY combo IP. This supports MIPI C-PHY v2.1 at 8.0Gsps per trio and MIPI D-PHY v2.5 at 6.5Gbps per lane. With 3 trios and 4 lanes, the IP supports over 54 Gbps aggregate bandwidth in C-PHY mode and 26 Gbps in D-PHY mode. At DAC, Mixel will have multiple customer demos featuring previous generations of its MIPI C-PHY/D-PHY combo IP. Hercules Microelectronics HME-H3 low-power FPGA leverages Mixel’s C-PHY/D-PHY combo RX IP and is in mass production. Hercules Microelectronics’s customers include Blackview which is in production with the HME-H3 FPGA in the Blackview Hero 10 foldable smartphone. Synaptics has also integrated Mixel’s MIPI C-PHY/D-PHY combo TX IP in Synaptics’s DisplayPort to dual MIPI VR bridge IC, the VXR7200.
Mixel has been focused on providing auto grade IP for many years. To further support its automotive customers, Mixel achieved ISO 9001 Quality Management System Certification and ISO 26262 certification for automotive functional safety. The Mixel MIPI product development process was certified up to ASIL-D with multiple products certified up to ASIL-B. Mixel will be showcasing one automotive customer demo from GEO Semiconductor (acquired by indie Semiconductor in 2023), the GEO GW5 geometric processor, featuring Mixel’s MIPI D-PHY CSI-2 TX and MIPI D-PHY CSI-2 RX IPs.
Mixel invites you to visit booth #2616 at DAC 2025, to meet their experts and explore how these technologies can benefit your SoC designs.
If you can’t make it DAC, you can learn more at https://mixel.com/
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