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Choose the Right ASIC Manufacturing Model for Your Business

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

REPLAY: The Brave New World of Customized Memory

REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning

REPLAY: VLSI Design Methodology Development

REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!

REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?

REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!

REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

REPLAY: Taiwan ESD Workshop Recording

REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction

REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)

REPLAY: Finding Your Way Through Verification

REPLAY: Concerned about IP security threats for your SoCs?

REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip

REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

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August 8, 2016September 23, 2019

MIPI DevCon 2016: Opened to non-MIPI Members!

MIPI DevCon 2016: Opened to non-MIPI Members!
by Eric Esteve on 08-08-2016 at 7:00 am
Categories: Automotive, IoT, Mixel, Mobile

The MIPI Alliance was founded in 2003 by large IDM to standardize chip-to-chip interfaces in the wireless phone (mobile) segment. The various MIPI specifications (CSI, DSI, DigRF and many more) have been adopted by the application processor chip makers (usually large IDM or fabless, like Intel or Qualcomm initially and many … Read More

February 22, 2012June 14, 2019

Don’t go to Mobile World Congress without “MIPI IP Forecast 2011-2016”!

Don’t go to Mobile World Congress without “MIPI IP Forecast 2011-2016”!
by Eric Esteve on 02-22-2012 at 9:48 am
Categories: Uncategorized

And if, like me, you don’t go to MWC, that’s the right time to get your version of the MIPI IP survey, the 3[SUP]rd[/SUP] version since the first launch in 2010, because IPNEST will give you a good reason to buy it during MWC: you will get it at a lower price. That will apply now and during the event, but only from today, and up to the 3[SUP]rd[/SUP]… Read More

December 14, 2009June 14, 2019

Semiconductor IP Innovation

Semiconductor IP Innovation
by Daniel Nenni on 12-14-2009 at 11:23 pm
Categories: IP

By definition:
Invention is a new composition, device, or process.
Innovation is a new way of doing something or “new stuff that is made useful”.
Image Removed
Even better:

Invention is the conversion of cash into ideas.

Innovation is the conversion of ideas into cash.

In an industry bound by technical standards and the law of physics,… Read More

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Recent Article Comments

A No-Fudge ML Architecture for Arm
Yes Kevin. Aligns with Arm embedded emphasis elsewhere. Would be a big departure for them to take on training, at…

— Bernard Murphy on November 15, 2019
Is the ASIC Business Dead?
It is not a bad exit per se. The acquisition agreement is up of the sec.gov website, and the financing…

— MarkK on November 14, 2019
A No-Fudge ML Architecture for Arm
You didn't stipulate, but assuming that Ethos is targeted at inference ?

— KevinK on November 14, 2019
ReRAM Revisited
Arthur - in reply to this accidentally misplaced question: Is this why TSM is concentrating on Crossbar to provide…

— Bernard Murphy on November 13, 2019
A No-Fudge ML Architecture for Arm
Arthur - I think you intended this comment for the ReRAM thread. I'll reply there

— Bernard Murphy on November 13, 2019
Is the ASIC Business Dead?
To Bernard: a model based on ASSP seems to see attraction. A Fabless who has already designed an ASSP…

— Eric Esteve on November 13, 2019
A No-Fudge ML Architecture for Arm
Is this why TSM is concentrating on Crossbar to provide on chip sophisticated memory? Will this advance if they…

— Arthur Hanson on November 13, 2019
Is the ASIC Business Dead?
Here is the Nirvana AI chip that eSilicon did: https://www.businesswire.com/news/home/20191112005277/en/Intel-Speeds-AI-Development-Deployment-Performance-New eSilicon did it for…

— Daniel Nenni on November 12, 2019
Is the ASIC Business Dead?
Talking about ASIC, we must split between "ASIC business" and "ASIC Technology". We know for long that…

— Eric Esteve on November 12, 2019
Is the ASIC Business Dead?
Ian has a good point on viability being in vertical integration. I wonder then who's handling all the systems silicon…

— Bernard Murphy on November 12, 2019

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Tag: mixel

MIPI DevCon 2016: Opened to non-MIPI Members!

Don’t go to Mobile World Congress without “MIPI IP Forecast 2011-2016”!

Semiconductor IP Innovation

Upcoming Events

Getting Started with ANSYS RedHawk

Digital Mission Engineering (Columbia, MD)

The 2019 Material Intelligence Seminar...

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Getting Started with ANSYS Totem

Search Semiwiki

Recent mixel Press

Mixel’s MIPI D-PHY IP Integrated into Microsoft’s Azure Kinect DK Depth Camera

Mixel Granted US Patent for its Innovative MIPI D-PHY RX+ Configuration

Mixel MIPI D-PHY IP Integrated into Teledyne e2v Snappy CMOS Image Sensors

Recent Article Comments

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

A No-Fudge ML Architecture for Arm

ReRAM Revisited

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

A No-Fudge ML Architecture for Arm

Is the ASIC Business Dead?

Is the ASIC Business Dead?

Is the ASIC Business Dead?