IP is the center of the semiconductor universe and nobody knows this better than Design and Reuse. The D&R website was launched in 1997 targeting the emerging commercial semiconductor IP market. Today, with more than 15,000 IP/SOC product descriptions updated daily, D&R is the #1 IP site matching customer requirements to IP products around the world.
D&R also hosts IP events including Semiconductor IP – SoC 2013 which will be the 22nd edition of the working conference on hot topics in the design world, focusing on IP-based SoC design and held in the French Alps (Grenoble) as well as Bejing, Shanghai, and Israel.
This event is the only worldwide dedicated semiconductor IP event. The satisfaction level of the attendees is high due to focused sessions and seminars. Over the year semiconductor IP has become Subsystems or Platforms. A natural applicative extension to IP-SoC will include a strong Embedded Systems track addressing a continuous technical spectrum from IP to SoC to Embedded System.
The competitive landscape of the Semiconductor IP Market, 2013 and Beyond!
Ganesh Ramamoorthy,Research Director, Gartner Inc.
Embedded design in the Age of Pervasive Computing
Richard York , Director of Embedded Processor Products, ARM
Open Innovation Platform (OIP): an ecosystem for innovation
Kees Jooss , Business Development Manager, TSMC
The New Tower of Babel – The Languages of Embedded Systems Design
Colin Walls, Mentor Graphics
Morphing Technology and Business Models at 100Gbps and Beyond
Marc Miller,Sr. Director of Marketing, Tabula
The flexible pathway to Flash IP
Christopher Neil Brown, Micro Chip
The conference is organized as a 2 day event:
- The first day targeting architecture topics from IP to SoC solution to chip and chip set
- The second day devoted to Embedded systems (from O.S to middleware to application software)
The program of both days is organized within within 4 tracks namely:
- The well recognized Panel track on hot topics. These panels will address both IP and Embedded Systems to day challenges
- Technical papers addressing the issues in the IP-based system design and in the Embedded System arenas
- Visionary scientific seminarson key topics organized by gurus in the field, including invited state of the art academic presentations
- Exhibitor track offering sponsored speaking opportunities for Companies willing to communicate their technical capabilities in greater depth ideas through technical presentations in one hour or in half-day workshops. Such a presentation slot may be a stand-alone demonstration of a development tool or technique
Important Dates
Deadline for submission of paper summary: September 28, 2013
Notification of acceptance: October 4, 2013
Final version of the manuscript: October 19, 2013
Working conference: November 6-7, 2013
Areas of interest:
Business models
- IP Exchange, reuse practice and design for reuse
- IP standards & reuse
- Collaborative IP based design
Design
- DFM and process variability in IP design
- IP / SoC physical implementation
- IP design and IP packaging for Integration
Quality and verification
- IP / SoC verification and prototyping
- IP / SoC quality assurance
Architecture and System
- IP based platform
- FPGA SoC
- IP / SOC transaction level modelling
- HW/SW integration
- System-level prototyping and virtual prototyping
- System-level prototyping and virtual prototyping
Embedded Software
- IP based platfrom
- Middelware
- O.S
Reliability, Real-Time and Fault Tolerant Systems
- IP reliability computation
- Security IP
- Real-time or Embedded Computing Platforms
- Real-time Operating system
Paper Submission Procedure
To present a paper during the conference a summary of at least 3 pages is required for any submission. You may also apply to present a seminar paper on the topics that will be announced shortly. You can submit an electronic version of your extended abstract in a Word or PDF format using the Online Submission Form.
lang: en_US
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