New Vivado release goes from Lab to UltraScale

Xilinx users will welcome the brand-new release of Vivado Design Suite 2015.1. For openers, device support for the latest FPGAs in the UltraScale family – XCVU440, XCVU190, and XCVU125 – has been added in the release, and early access code for the XCVU160 is available from a local Xilinx FAE. Installation has been streamlined, removing the need for root or sudo privileges on Linux for the suite, with a new dedicated script for handling cable drivers manually as an option if needed. Borrowable, floating FlexLM license support is improved in this release, and a new standalone hardware microserver (it’s small, less than 1% of the code for the total product) handles remote debug over Ethernet, easing distributed development.

One of the biggest new features in this version is actually … a variant with fewer features, available free of charge. Sometimes, all one needs to do is program and debug a part, like in test or academic environments. Now, a new lightweight edition – Vivado Lab Edition – does just that and nothing else. It comes in a 75% smaller, 1GB download, doesn’t require license keys or activation, and supports all the same Xilinx devices of the full suite.

For development users who crave the full-price Vivado Design Suite and the latest feature enhancements, this release has those as well. The need for speed has been addressed, with improved simulation script algorithms that speed up compile time by 2 to 2.5x. This and other improvements yield 20 percent faster simulations than previous Vivado releases, and an order of magnitude improvement in simulator disk footprint. Using the Vivado TCL store infrastructure, this version integrates with Aldec Riviera-PRO for more advanced simulation, as well as with simulation flows from Cadence, Mentor, and Synopsys.

With the extensive changes in the UltraScale clocking structure and far more clock regions in the part, the likelihood of clock domain crossings (CDCs) in a large FPGA design continues to increase. CDC detection in this Vivado release now spots 16 typical topologies, with summaries by clock pair or by rule type with cross probing to schematic and RTL.

There are also new enhancements for Zynq-7000 All Programmable SoC developers, with additions to analyze performance of the processor subsystem (PS) and the bandwidth used between the PS, the programmable logic (PL), and external memories. System model designs with AXI traffic generators are also provided for the ZC702 and ZC706 evaluation boards.

The partial reconfiguration feature introduced previously has been further expanded, including UltraScale support. There are numerous improvements in IP and its integration, and changes specific to IP leveraging UltraScale features. Among new IP in the release is a block for UHD-SDI video in several SMPTE formats.

Noteworthy is for the full-featured Vivado Design Suite 2015.1, 32-bit operating system support has been removed. This allows performance optimization for design entry and implementation to move forward. Vivado Lab Edition 2015.1 is still supported on older development hosts such as Windows 7 and Red Hat Enterprise Linux 6.

Vivado users should head for http://www.xilinx.com/download to get their new version, including the hardware microserver, documentation navigator, and license management tools. A short video highlighting many of these changes is also available at

What’s New in Vivado 2015.1