Marie Semeria is the CEO of Leti, one of the world’s premier research organization for semiconductor technology and the key development center for FDSOI. I first interviewed Marie at SEMICON West and at IEDM I had a chance to sit down with her and get an update on Leti’s efforts over the last several months.
My interview with Marie at SEMICON West is available here.
FDSOI
When I spoke to Marie at SEMICON West we discussed the long-term roadmap for FDSOI with extendibility down to 10nm and even 7nm. At the time GLOBALFOUNDRIES had announced their 22FDX technology and that there would be a follow on FDSO technology but had not announced what it would be. At that time Marie noted that Leti was working with GLOBALFOUNDRIES, since then GLOBALFOUNDRIES has announced 12FDX as their next generation technology. Marie noted that Leti continues to work with GLOBALFOUNDRIES to make 22FDX happen, design 12FDX and implement the required ecosystems.
In September it was announced that Sony has developed a smart watch GPS chip with ST Micro on FDSOI. The chip provides 10x the battery life of a bulk chip and the watch utilizing the chip will be announced in the USA and Europe next month. In September GLOBALFOUNDRIES also announced 60 tape outs and Samsung has 16 tape outs on FDSOI. Approximately one half of the tape outs should be products 18 months later, several products should appear at the end of next year.
One of the key attributes of FDSOI is the revolutionary ability to tune the wafers after they come out of the fab using biasing. Designers need to be trained to use back biasing and Leti has designed specific IP for this application. GLOBALFOUDNRIES has an initiative to have a complete design and IP ecosystem and Leti is involved in making this happen.
ST Micro is capitalizing on 28nm FDSOI for MCU and automotive applications. FDSOI inherent radiation hardness makes it ideal for automotive applications.
Another strength of FDSOI is in the RF space where FDSOI has >2x the performance of FinFETs. LETI has already reported FT/Fmax=390/385GHz at 28nm, good analog performance and reduced noise and good RF efficiency of the back gate yielding good RF designs. FinFETs low Ft is mainly impacted by strong parasites capacitances and Fmax mainly impacted by Gate resistance (Gate last process)
One of the biggest collaborations for Leti in FDSOI is with Soitec to optimize the substrates. It is very important to be able to give Soitec the device feedback and understand the impact of the substrate on the device and to be able to understand the contribution of the device and the substrate.
Leti is also working on new ways to leverage FDSOI and at IEDM presented a paper on integrating a photodiode under the Box layer to generate bias under the Box.
Horizontal Nanowires
Horizontal Nanowires (HNW) is an area of intense research in the industry. Both FinFETs and FDSOI devices are facing fundamental scaling issues around the 7nm node and are reaching thickness and electrostatic control limits. HNWs have a process very similar to FinFET formation and represent an evolutionary path with superior electrostatics. Leti has been working on HNW for 10 years whereas IMEC started with vertical nanowires before switching to HNW more recently.
Similar to the FDSOI work described in my SEMICON article (see above), Leti develops models of HNW, then they build test devices and calibrate and confirm the model to give confidence to model based projections. Leti has a long history of stressors in the substrate and S/D and they can carry that over to HNW. They have the full model that has been confirmed and characterized to use for HNW.
Leti has two HNW efforts, one with ST Micro and relaxed geometries and one with IBM at scale. Leti has presented a compact model of HNW stress they developed with IBM. The model integrates quantum effects and stress and is confirmed by experimental data. Their experience in stressors is very useful for tuning very advanced devices
At IEDM Leti presented a paper on a stacked HNW technology with raised source/drains including for the first time a silicon germanium (SiGe) raised S/D to strain the pFET channel. The pFET had a SiGe:B (boron doped SiGe) raised S/D and the nFET had a Si:P (phosphorus doped silicon) raised S/D. They used an inner spacer and wet etch to etch out the SiGe layers releasing the Si nanowire while protecting the SiGe:B raised S/D.
The basic process flow is:
- Super lattice deposition (alternating SiGe and Si layers)
- Fin patterning – similar to FinFET process except that two different materials are etched
- Dummy gate formation – similar to FinFET
- Spacer formation – similar to FinFET
- Inner spacer formation – CD recess with wet etch, second deposition and etch back to form a spacer in the recess
- Source/drain epi – similar to FinFET
- ILD and CMP – similar to FinFET
- Dummy gate removal – similar to FinFET
- Nanowire release etch – wet etch
- Gate stack formation – similar to FinFET
- Contact and back end of line – similar to FinFET
As can be seen from the process flow above, only a few steps are different from FinFET processing although the difficulty of the integration issues should not be underestimated.
Non-Volatile Memory
Leti has developed a test vehicle for comparing nonvolatile memory: MRAM, OXRAM, PCRAM, CBRAM on the same test vehicle. They are working to benchmark and optimize the nonvolatile memory for each design. RRAM is interesting for computing application. With Spintech they are working on MRAM. They have set up a roadmap to very low power MRAM using a new type of spin. They are working with GLOBALFOUNDRIES and Samsung on MRAM and ST Micro on PCRAM.
Conclusion
In conclusion Leti is working with GLOBALFOUNDRIES, Samsung, Soitec and ST Micro to commercialize FDSOI while also pursing next generation HNW and nonvolatile memory technologies for future generations.
Also Read:
CEO Interview: Dündar Dumlugöl of Magwel
CEO Interview: Jack Harding of eSilicon
CEO Interview: Randy Caplan of Silicon Creations
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