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DAC luncheon: Improve the fidelity of ESD margins and leakage flows
DAC luncheon: Improve the fidelity of ESD margins and leakage flows
Conservative design rules and constraints are often used in reliability verification flows. By combining the leading solutions provided by Siemens Calibre PERC and SPICE simulation technologies, SPICE-accurate full-chip simulation becomes possible in a compelling flow for design teams looking to better understand their ESD design margins. For analog designers, we will explore exciting challenges and …
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