3DIC in Burlingame

Every year in December is what I think of as the main 3D IC conference where you can get up to speed on all the latest. Officially it is called 3D Architectures for Semiconductor and Packaging or 3D ASIP. It is held in the Hyatt Regency in Burlingame (the one right by 101 near the airport). This year it is from December 10-12th.

The first day is a pre-conference symposium. In the morning Herb Reiter is the master of ceremonies for a session on 3D-IC design tools and flows, with presentations by Bill Martin of eSystem Design, Zafer Kutlu of GlobalFoundries, Brandon Wang of Cadence, Norman Chang of ANSYS/Apache, John Ferguson of Mentor, Ming Li of Rambus, Durodami Lisk of Qualcomm and Jerry Frenckil of Si2.

That afternoon Herb passes the baton to Phil Garrou for a discussion of 3D Process Technology. Dean Malta of RTI will talk ab out TSV Formation. Severine Cheramy of CEA Leti will talk about Temporary Bonding and Via Reversal. Laura Mirkarimi of Invensas will talk about the rather broad topic of Assembly.

The conference proper starts on Thursday December 11th at 8am. The opening keynote sessions are:

• Steve Schultz of Si2 titled A Design Ecosystem for Internet of Things, How 3D IC Standards will Enable a New Growth Paradigm. He will talk about how IoT will be a driver for 3D and how important standards will be to making it happen in a timely manner.
• Robert Sturgill of Micron on 2.5D and 3D Memory Solutions and Outlook. Micron builds the hybrid memory cube which has 4 memory die on top of a logic die, and so arguably they have as much experience at 3D in a commercial context as anyone.
• Xin Wu of Xilinx on An Ultrascale 3D FPGA. Xilinx built what is regarded as the first 2.5D chip in commercial production. Since it is a very high end FPGA it does not ship in enormous volume nor does it have to meet a consumer price point, but it was clearly an experiment to serve as a learning vehicle.

The next session isIoT, Memory and More than Moore with presentations from Yole Development, GE, Novati and NVIDIA.

After lunch, it is on to Perspectives on Manufacturing and Cost with presentations from Techsearch, Invensas and SavanSys Solutions. Since the main issues in 3D seem to be more around getting the cost down more than the technology of 3D manufacturing (we know how to make TSVs pretty well) this should be an interesting session.

Herb then will moderate a panel with Qualcomm, Atrenta, EVG and UC Santa Barbara on how to further strengthen 2.5D/3D IC pathfinding.

Finally, to wrap up the day, Ansys/Apache and Synopsys will talk about modeling, signal integrity and more.

On Friday we start by dropping half a dimension with a session on 2.5D interposers, with presentations from GlobalFoundries, Nanium, CEA-Leti, RTI International and Unimicron.

There is then a session on monolithic 3D, which is not building separate die and then using TSV to stack them but rather building a 3D chip by laying down more and more layers on a starting wafer. Presentations are by CEA-Leti, EV Group and Monolithic 3D.

The final session is 2.5/3D Systems — Bringing It All Together. There are presentations from Fraunhofer Institute for ICs, ON Semiconductor and IBM TJ Watson Research.

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