If you are ever asked to organize a conference session do not hesitate, accept immediately and jump right in. When John Swan, EDPS General Chair, asked me to organize a day I hesitated. Fortunately he is not one to take no for an answer. It was an unforgettable experience on many levels and I hope to be involved with EDPS again next year. Yes it was that good.
First the location, Monetery is absolutely the best place for a conference. The hotel was right on the beach with the most amazing views. The weather was excellent, the hotel food was excellent, it was one of the most relaxing and informative weekends I have had in a long time. I have always pushed for more convenient conference locations to get the highest attendance but I was wrong. Quality over quantity, location, location, location and Monterey is a great place.
Picking the topic and presenters for a conference should probably be a stressful thing but it was what I enjoyed the most. FinFET was the most written about subject and top trending search term on SemiWiki in 2012 so that was easy. The presenters were people I know and respect so that was also easy. Organizing and coordinating the day took much more time than I had imagined but it was well worth the effort.
Here’s how the day played out:
I did a quick 15 minute keynote to set the day up with my FinFET experiences and SemiWiki analytics. My good friend Tom Dillinger finished the keynote with a Primer on FinFETswhich was a perfect set-up for the rest of the day. Tom has been a great technical back-up on FinFETs including the FinFET Wikion SemiWiki. Tom is also a great speaker, the author of VSLI Engineering circa 1987, and an expert in this field.
After the break Tom did his presentation on FinFET parasitics, which as it turns out, is one of the biggest challenges facing FinFET designers today and tomorrow. Thank you Tom, you hit this one out of the park.
Next up was Rob Aitken. I first met Rob at Artisan many years ago and he is now an R&D Fellow at ARM. Rob presented FinFET SoC Design Challenges which included a Silicon Device Roadmap down to .35nm which may not have any actual silicon content. What!?!?!?!?!
Next up was Raymond Leung. I first met Raymond when he was VP of Engineering at Virage Logic. We met up again when he was VP of Memory Development at UMC and now he is VP of Engineering at Synopsys. Raymond presented on FinFETs and SRAM Design. Since SRAMs are the pipe cleaners for new semiconductor processes and Synopsys is the top SRAM provider, Raymond has seen the most 16/14nm silicon thus far. He presented FinFET design challenges in great detail and who would know better than Raymond.
Tom Quan finished the session with FinFET Design Ecosystem Challenges and Solutions. Tom is a great presenter and clearly distinguishes between marketing and silicon correlated data. According to Tom the value proposition of FinFETs versus Planar at 20nm is up to 20% performance at the same power consumption, 35% savings in power at the same speed, and 1.1X density. Those my friends are great numbers!
As I mentioned before, FinFETs are the most interesting technology we will see this decade so it was a day well spent. My wife and I stayed on an extra day to enjoy Monterey, which was where we spent our second wedding anniversary many years ago.
Please post your EDPS 2013 Monterey questions, comments, and trip reports HERE!
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