Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design

The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques.

For the past years, Synopsys and Ansys have been creating design flows that carry designers through early exploration, implementation, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market.

Register now to learn about:

– Multi-die design best practices for thermal, signal, and power integrity

– Insights from practical multi-die design case studies

– More advanced packaging technologies for thermal management, backside power, and co-packaged optics

SPEAKERS

Marc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose, CA. Before joining Ansys, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys, Azuro, and Sequence Design, where he gained experience with a wide array of digital and analog design tools.

Keith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design, analog/mixed signal (AMS) and RF/mmWave product experience, including 8 years designing high speed data converters and amplifiers at Analog Devices.

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