Achieving Design Robustness in Signoff for Advanced Node Digital Designs

I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all know how difficult that can be at the cutting edge. Presented by Synopsys, the webinar explores strategies to make the process of hierarchical extraction and timing analysis (StarRC) for advanced node designs more accurate and efficient.

Hierarchical design is a key element in the “divide and conquer” approach to dealing with large amounts of complex design data. But there are some very real and challenging problems to overcome to use this technique effectively for advanced node designs. Here are just a few of them:

• For extraction, you need to consider capacitance interactions across hierarchical boundaries. For example, near-the-block or over-the-block top level routes and block-to-block coupling
• For process variation, you need to consider boundary nets that are impacted by nets running close to the boundary at the top level
• Due to CMP, block instances may have unique layout environment densities that need to be accounted for
• There may be multiple physical ports at the block level that map to one logical port. Extraction and timing flows need to correctly map physical and logical pins
• The number of process, temperature, via resistance and other corners is exploding. You need a way to process all these cases efficiently
• Also, regarding corner analysis, typical foundry data varies metal thickness in the same direction. This is not realistic in many cases, where metal thickness can vary across the chip. Not modeling this effect can miss timing violations

If you are engaged in advanced node design, I highly recommend attending this webinar. You will learn about approaches to deal with all of items above and more. You’ll learn about new approaches to optimize the run-time of the required tools as well. There is also a very useful Q&A session that dives into a lot more detail. All of this is covered in just over 30 minutes.

The webinar presenter is Omar Shah, who has 20 years of experience working on post-layout digital and custom design flows. Sign up now to attend this webinar. The webinar will be broadcast on Tuesday, March 24, 2020 from 10:00 AM – 11:00 AM PDT.  Hand sanitizer and face mask not required.

About StarRC
StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

Also Read:

Navigating Memory Choices for Your Next Low-Power Design

Hybrid Verification for Deep Sequential Convergence

Edge Computing – The Critical Middle Ground