Tag: advanced node

Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process

Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process
by Admin on 05-10-2024 at 2:15 pm

Synopsys’ SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle.

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Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Mike Gianfagna on 03-09-2020 at 10:00 am
Categories: EDA, Events, Synopsys

Synopsys SemiWiki STARRC Webinar 1

I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More

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High Calibre Development Keeps Mentor on Top of the Game

High Calibre Development Keeps Mentor on Top of the Game
by Tom Simon on 12-07-2017 at 12:00 pm
Categories: EDA, FinFET, Siemens EDA

One might be tempted to think that technology driven gains in computer performance might be enough to keep up with the needs of design and verification tools. We know that design complexity is increasing at a rate predicted by Moore’s Law. We also know that the performance of the computers used during IC development benefit from … Read More