Deploying 14nm FinFETs in your Next Mobile SoC

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

• Ed Sperling, Semi Mfg and Design
• Anil Jain, Cavium
• Subramani Kengeri, GLOBALFOUNDRIES
• Kelvin Low, GLOBALFOUNDRIES
• Raymond Leung, Synopsys
• Bari Biswas, Synopsys

Notes

Ed – Why use 14nm FinFETs? Improved leakage, better layout density benefits.

Anil – How do designers see the benefits? Make FinFETS transparent to the designers. Cavium started in 2001, IPO in 2007 and 650 engineers, networking, communication and data centers. Use MIPS 64, ARM 64, NITROX.

– Planar CMOS running out of steam. Slower performance increases. Little power and voltage scaling. Sub-threshold leakage too great. Variation across wafer too great.

– FinFET benefits: ION increases. Fully depeleted devices improve sub-threshold leakage. Lower Vt is possible to scale. Reduced vaiation.

– FinFETabout 10X better for sub-threshold leakage.

– Short channel effects are reduced with FinFETS, better stacking properties.

– High fanin circuits are possible with FinFETs and switch faster than planar.

– Vt can be adjusted lower.

– Downside of FinFETS: gate capacitance per unit area goes up. Gate parasitics go up. Dynamic power is not scaling as much, too much capacitance.

– EM gets worse with FinFET, because of increased current drives

Subramani – engineering on FinFET for the past 10 years.
– Mobile SoCs have the highest CAGR, so is driving technology.
– Issues: Power density, BEOL RC, cost, ttv (time to volume)

R&D – high K, metal gate (gate last), eSiGe (Stress engineering), litho with DPT and 193nm immersion. In the labs for 10 years now, development alliance.

optimization – Fin width is quantized, limits IC design choice.
– 3d structure makes RC more complex to calculate
– EDA flow: DRC, LVS, SPICE model, DPT aware placement and routing
– higher number of process variations

TCAD optimization – hight of FinFET, pitch, width, lower Vdd values possible. SRAM can run 250mv lower than planar. About 20% performance benefit in 14nm finfet over 20nm planar. Area reduction of 5%. ARM with 16% power improvement, or 16% speed improvement.

Raymond Leung – synopsys
IP development and FinFET technology
LDE has increased with each new node, another doubling from 20nm to 14nm.
Requires a technology assessment test chip to evaluate.
– Designers use new BSIM models with quantized and L, NF, NFIN, etc. BSIM4 CMG is used.
– SRAM designs are not direct ports from planar, no body bias allowed..
– Layout migration not possible from planar to FinFET.
– HCI and SER improved, while NBTI is worse in FinFET.
– Many years of FinFET IP design experience, 2005.
– Better current drive seen, lower VDD used, lower power consumption.
– IC layout is more complex with FinFET, requires closer collaboration with foundry. Iterate between circuit design, layout, simulate, iterate. Instead, plan ahead for IC layout at circuit design stage.
Collaboration between GF and SNPS – SRAM bit cell study. IC layout reviews. SPICE model evaluation from an IP viewpoint. ROM bit cell for optimum density, single mask programmable. Memory pin optimization for DPT issues. Std cell review and process co-optimization.
– Memory compilers coming soon: high speed, high density, ultra high density.
– std cell libraries, high speed high density, multi-channel, power optimized kits, datapath. About 1000 cells

Bari Biswas (Tools and flows)
Front End Of Line (FEOL)
Middle End of LIne (MEOL) – StarRC, HSPICE, TCAD
Back End of LIne (BEOL) – interconnect. ICC/ICV, StarRC, DPT
TCAD – accurate modeling goal, very complex device and interconnect profiles.
HSPICE – uses BSIM-CMG models from UC Berkeley
– Well Proximity Effect is in HSPICE and CustomSim
– Parasitic extraction with StarRC, how to extract accurately and scale for billions of transistors. DOn’t double count Capacitance between device model and interconnect.

Interconnect Technology Format (ITF) – used for multi-gate definition.

IC Compiler – odd cycle detection and avoidance. Cell placement takes DFM into account. EM effects calculated during P&R.

Kelvin Low, GF
14nm silicon cross section photos.
Mobile phone users want multi-day battery life.
Compute, connect and storage markets will use FinFET to reduce power in data servers.
Summary of previous speaker points.
DPT – support both color-less and color layout styles.
Expect an AMS reference flow and 2.5D reference flow.
Deeper and earlier collaboration with EDA, IP and Foundry required.

Q&A:
What were the biggest design challenges?
Anil: SRAM design bit cells come from the foundry, however designing our datapaths we have to use width quantized thinking. PMOS devices are stronger now, both NAND and NOR devices.

What about EUV?
Subramani – Technically we can add triple and quad patterning with newer nodes. Financially, we are in trouble with multi-patterning. EUV will get to production, but at what costs?

Does variation go down or up?
Anil – fully depleted devices have less Vt variations.
Subramani – parasitics variation goes up.

What about the thermal issues with FinFET?
Raymond – local heating or self heating have to be dealt with. Has to be designed around.

Are you optimizing the metal stack?
Bari – yes, both the device and interconnect parasitics go up. DPT causes mask misalignment, more RC variations.
Subramani – An 80nm metal is offered to lower the RC delays.
Kelvin – TCAD experiments were run to optimize for GPU designs.

What about FD SOI instead of FinFET?
Subramani – FinFET is also fully depleted, like FD SOI. It really depends on your application, because FD SOI has lower capacitance and lower drives.

Share this post via:

• 
• 
• 
•